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misched: Better handling of invalid latencies in the machine model

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-10-17 17:27:10 +00:00
parent a747a84add
commit fdd6fa89b9
2 changed files with 15 additions and 5 deletions
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8
include/llvm/MC/MCSchedule.h
View File

@ -54,10 +54,12 @@ struct MCWriteProcResEntry {
}; };
/// Specify the latency in cpu cycles for a particular scheduling class and def /// Specify the latency in cpu cycles for a particular scheduling class and def
/// index. Also identify the WriteResources of this def. When the operand /// index. -1 indicates an invalid latency. Heuristics would typically consider
/// expands to a sequence of writes, this ID is the last write in the sequence. /// an instruction with invalid latency to have infinite latency. Also identify
/// the WriteResources of this def. When the operand expands to a sequence of
/// writes, this ID is the last write in the sequence.
struct MCWriteLatencyEntry { struct MCWriteLatencyEntry {
unsigned Cycles; int Cycles;
unsigned WriteResourceID; unsigned WriteResourceID;
bool operator==(const MCWriteLatencyEntry &Other) const { bool operator==(const MCWriteLatencyEntry &Other) const {

12
lib/CodeGen/TargetSchedule.cpp
View File

@ -58,6 +58,14 @@ unsigned TargetSchedModel::getNumMicroOps(MachineInstr *MI) const {
return MI->isTransient() ? 0 : 1; return MI->isTransient() ? 0 : 1;
} }
// The machine model may explicitly specify an invalid latency, which
// effectively means infinite latency. Since users of the TargetSchedule API
// don't know how to handle this, we convert it to a very large latency that is
// easy to distinguish when debugging the DAG but won't induce overflow.
static unsigned convertLatency(int Cycles) {
return Cycles >= 0 ? Cycles : 1000;
}
/// If we can determine the operand latency from the def only, without machine /// If we can determine the operand latency from the def only, without machine
/// model or itinerary lookup, do so. Otherwise return -1. /// model or itinerary lookup, do so. Otherwise return -1.
int TargetSchedModel::getDefLatency(const MachineInstr *DefMI, int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
@ -178,7 +186,7 @@ unsigned TargetSchedModel::computeOperandLatency(
const MCWriteLatencyEntry *WLEntry = const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx); STI->getWriteLatencyEntry(SCDesc, DefIdx);
unsigned WriteID = WLEntry->WriteResourceID; unsigned WriteID = WLEntry->WriteResourceID;
unsigned Latency = WLEntry->Cycles; unsigned Latency = convertLatency(WLEntry->Cycles);
if (!UseMI) if (!UseMI)
return Latency; return Latency;
@ -219,7 +227,7 @@ unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
// Lookup the definition's write latency in SubtargetInfo. // Lookup the definition's write latency in SubtargetInfo.
const MCWriteLatencyEntry *WLEntry = const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx); STI->getWriteLatencyEntry(SCDesc, DefIdx);
Latency = std::max(Latency, WLEntry->Cycles); Latency = std::max(Latency, convertLatency(WLEntry->Cycles));
} }
return Latency; return Latency;
} }