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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
Grab the subtarget off of the machine function for the R600
asm printer and clean up a bunch of uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229803 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -58,7 +58,7 @@ using namespace llvm;
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// instructions to run at the double precision rate for the device so it's
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// instructions to run at the double precision rate for the device so it's
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// probably best to just report no single precision denormals.
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// probably best to just report no single precision denormals.
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static uint32_t getFPMode(const MachineFunction &F) {
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static uint32_t getFPMode(const MachineFunction &F) {
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const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
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// TODO: Is there any real use for the flush in only / flush out only modes?
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// TODO: Is there any real use for the flush in only / flush out only modes?
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uint32_t FP32Denormals =
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uint32_t FP32Denormals =
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@ -112,7 +112,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
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Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
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OutStreamer.SwitchSection(ConfigSection);
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OutStreamer.SwitchSection(ConfigSection);
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
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SIProgramInfo KernelInfo;
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SIProgramInfo KernelInfo;
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if (STM.isAmdHsaOS()) {
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if (STM.isAmdHsaOS()) {
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getSIProgramInfo(KernelInfo, MF);
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getSIProgramInfo(KernelInfo, MF);
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@ -178,10 +178,10 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
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void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
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unsigned MaxGPR = 0;
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unsigned MaxGPR = 0;
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bool killPixel = false;
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bool killPixel = false;
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const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
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const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
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TM.getSubtargetImpl()->getRegisterInfo());
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const R600RegisterInfo *RI =
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static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
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const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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for (const MachineInstr &MI : MBB) {
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@ -237,15 +237,15 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
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void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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const MachineFunction &MF) const {
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const MachineFunction &MF) const {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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uint64_t CodeSize = 0;
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uint64_t CodeSize = 0;
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unsigned MaxSGPR = 0;
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unsigned MaxSGPR = 0;
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unsigned MaxVGPR = 0;
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unsigned MaxVGPR = 0;
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bool VCCUsed = false;
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bool VCCUsed = false;
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bool FlatUsed = false;
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bool FlatUsed = false;
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const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
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const SIRegisterInfo *RI =
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TM.getSubtargetImpl()->getRegisterInfo());
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static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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for (const MachineInstr &MI : MBB) {
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@ -416,7 +416,7 @@ static unsigned getRsrcReg(unsigned ShaderType) {
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void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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const SIProgramInfo &KernelInfo) {
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const SIProgramInfo &KernelInfo) {
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
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unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
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@ -454,7 +454,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
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void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
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void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
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const SIProgramInfo &KernelInfo) const {
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const SIProgramInfo &KernelInfo) const {
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
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amd_kernel_code_t header;
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amd_kernel_code_t header;
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memset(&header, 0, sizeof(header));
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memset(&header, 0, sizeof(header));
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@ -92,13 +92,12 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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}
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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AMDGPUMCInstLower MCInstLowering(OutContext,
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const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
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MF->getSubtarget<AMDGPUSubtarget>());
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AMDGPUMCInstLower MCInstLowering(OutContext, STI);
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#ifdef _DEBUG
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#ifdef _DEBUG
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StringRef Err;
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StringRef Err;
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if (!MF->getSubtarget<AMDGPUSubtarget>().getInstrInfo()->verifyInstruction(
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if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
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MI, Err)) {
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errs() << "Warning: Illegal instruction detected: " << Err << "\n";
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errs() << "Warning: Illegal instruction detected: " << Err << "\n";
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MI->dump();
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MI->dump();
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}
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}
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@ -116,7 +115,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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MCInstLowering.lower(MI, TmpInst);
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MCInstLowering.lower(MI, TmpInst);
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EmitToStreamer(OutStreamer, TmpInst);
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EmitToStreamer(OutStreamer, TmpInst);
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if (MF->getSubtarget<AMDGPUSubtarget>().dumpCode()) {
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if (STI.dumpCode()) {
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// Disassemble instruction/operands to text.
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// Disassemble instruction/operands to text.
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DisasmLines.resize(DisasmLines.size() + 1);
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DisasmLines.resize(DisasmLines.size() + 1);
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std::string &DisasmLine = DisasmLines.back();
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std::string &DisasmLine = DisasmLines.back();
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