From fde5f801be6bb75fad4e7a39b5bc62c04857ac0c Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sun, 30 Dec 2007 21:01:27 +0000
Subject: [PATCH] Simplify and clean up some machine operand/instr
 printing/dumping stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45456 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/MachineInstr.cpp | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index e8f692e15f8..49ceab70415 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -267,15 +267,16 @@ void MachineInstr::dump() const {
   cerr << "  " << *this;
 }
 
-static inline void OutputReg(std::ostream &os, unsigned RegNo,
-                             const MRegisterInfo *MRI = 0) {
-  if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
+static void OutputReg(std::ostream &os, unsigned RegNo,
+                      const MRegisterInfo *MRI = 0) {
+  if (MRegisterInfo::isPhysicalRegister(RegNo)) {
     if (MRI)
       os << "%" << MRI->get(RegNo).Name;
     else
-      os << "%mreg(" << RegNo << ")";
-  } else
+      os << "%mreg" << RegNo;
+  } else {
     os << "%reg" << RegNo;
+  }
 }
 
 static void print(const MachineOperand &MO, std::ostream &OS,
@@ -287,6 +288,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     OutputReg(OS, MO.getReg(), MRI);
+    if (MO.isDef()) OS << "<d>";
     break;
   case MachineOperand::MO_Immediate:
     OS << MO.getImm();
@@ -384,11 +386,8 @@ void MachineInstr::print(std::ostream &os) const {
   // and such.
   os << getInstrDescriptor()->Name;
 
-  for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
+  for (unsigned i = 0, N = getNumOperands(); i < N; i++)
     os << "\t" << getOperand(i);
-    if (getOperand(i).isRegister() && getOperand(i).isDef())
-      os << "<d>";
-  }
 
   os << "\n";
 }
@@ -397,6 +396,7 @@ void MachineOperand::print(std::ostream &OS) const {
   switch (getType()) {
   case MO_Register:
     OutputReg(OS, getReg());
+    if (isDef()) OS << "<d>";
     break;
   case MO_Immediate:
     OS << getImm();