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BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99423 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3613,6 +3613,54 @@ X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
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return SDValue();
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return SDValue();
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}
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}
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static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
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DebugLoc &dl, SelectionDAG &DAG) {
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EVT EltVT = VT.getVectorElementType();
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unsigned NumElems = Elts.size();
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// FIXME: check for zeroes
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LoadSDNode *LDBase = NULL;
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unsigned LastLoadedElt = -1U;
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for (unsigned i = 0; i < NumElems; ++i) {
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SDValue Elt = Elts[i];
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if (!Elt.getNode() ||
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(Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
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return SDValue();
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if (!LDBase) {
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if (Elt.getNode()->getOpcode() == ISD::UNDEF)
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return SDValue();
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LDBase = cast<LoadSDNode>(Elt.getNode());
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LastLoadedElt = i;
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continue;
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}
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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LoadSDNode *LD = cast<LoadSDNode>(Elt);
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if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
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return SDValue();
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LastLoadedElt = i;
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}
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if (LastLoadedElt == NumElems - 1) {
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if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
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return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
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LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
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LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
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return DAG.getLoad(VT, dl, LDBase->getChain(), LDBase->getBasePtr(),
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LDBase->getSrcValue(), LDBase->getSrcValueOffset(),
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LDBase->isVolatile(), LDBase->isNonTemporal(),
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LDBase->getAlignment());
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} else if (NumElems == 4 && LastLoadedElt == 1) {
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
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SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
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}
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return SDValue();
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}
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SDValue
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SDValue
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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DebugLoc dl = Op.getDebugLoc();
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@ -3841,14 +3889,18 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
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return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
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}
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}
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if (Values.size() > 2) {
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if (Values.size() > 1 && VT.getSizeInBits() == 128) {
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// If we have SSE 4.1, Expand into a number of inserts unless the number of
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// Check for a build vector of consecutive loads.
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// values to be inserted is equal to the number of elements, in which case
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for (unsigned i = 0; i < NumElems; ++i)
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// use the unpack code below in the hopes of matching the consecutive elts
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V[i] = Op.getOperand(i);
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// load merge pattern for shuffles.
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// FIXME: We could probably just check that here directly.
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// Check for elements which are consecutive loads.
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if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
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SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
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getSubtarget()->hasSSE41()) {
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if (LD.getNode())
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return LD;
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// For SSE 4.1, use inserts into undef.
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if (getSubtarget()->hasSSE41()) {
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V[0] = DAG.getUNDEF(VT);
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V[0] = DAG.getUNDEF(VT);
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for (unsigned i = 0; i < NumElems; ++i)
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for (unsigned i = 0; i < NumElems; ++i)
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if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
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if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
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@ -3856,7 +3908,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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Op.getOperand(i), DAG.getIntPtrConstant(i));
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Op.getOperand(i), DAG.getIntPtrConstant(i));
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return V[0];
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return V[0];
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}
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}
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// Expand into a number of unpckl*.
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// Otherwise, expand into a number of unpckl*
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// e.g. for v4f32
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// e.g. for v4f32
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// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
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// Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
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// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
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// : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
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@ -3871,7 +3924,6 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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}
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}
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return V[0];
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return V[0];
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}
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}
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return SDValue();
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return SDValue();
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}
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}
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@ -8797,83 +8849,24 @@ bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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return TargetLowering::isGAPlusOffset(N, GA, Offset);
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return TargetLowering::isGAPlusOffset(N, GA, Offset);
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}
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}
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static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
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EVT EltVT, LoadSDNode *&LDBase,
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unsigned &LastLoadedElt,
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SelectionDAG &DAG, MachineFrameInfo *MFI,
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const TargetLowering &TLI) {
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LDBase = NULL;
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LastLoadedElt = -1U;
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for (unsigned i = 0; i < NumElems; ++i) {
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if (N->getMaskElt(i) < 0) {
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if (!LDBase)
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return false;
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continue;
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}
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SDValue Elt = DAG.getShuffleScalarElt(N, i);
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if (!Elt.getNode() ||
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(Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
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return false;
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if (!LDBase) {
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if (Elt.getNode()->getOpcode() == ISD::UNDEF)
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return false;
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LDBase = cast<LoadSDNode>(Elt.getNode());
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LastLoadedElt = i;
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continue;
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}
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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LoadSDNode *LD = cast<LoadSDNode>(Elt);
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if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
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return false;
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LastLoadedElt = i;
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}
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return true;
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}
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/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
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/// PerformShuffleCombine - Combine a vector_shuffle that is equal to
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/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
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/// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
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/// if the load addresses are consecutive, non-overlapping, and in the right
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/// if the load addresses are consecutive, non-overlapping, and in the right
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/// order. In the case of v2i64, it will see if it can rewrite the
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/// order.
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/// shuffle to be an appropriate build vector so it can take advantage of
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// performBuildVectorCombine.
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static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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const TargetLowering &TLI) {
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const TargetLowering &TLI) {
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DebugLoc dl = N->getDebugLoc();
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DebugLoc dl = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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EVT EltVT = VT.getVectorElementType();
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ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
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ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
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unsigned NumElems = VT.getVectorNumElements();
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if (VT.getSizeInBits() != 128)
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if (VT.getSizeInBits() != 128)
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return SDValue();
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return SDValue();
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// Try to combine a vector_shuffle into a 128-bit load.
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SmallVector<SDValue, 16> Elts;
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
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LoadSDNode *LD = NULL;
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Elts.push_back(DAG.getShuffleScalarElt(SVN, i));
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unsigned LastLoadedElt;
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if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
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MFI, TLI))
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return SDValue();
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if (LastLoadedElt == NumElems - 1) {
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return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
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if (DAG.InferPtrAlignment(LD->getBasePtr()) >= 16)
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return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
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LD->getSrcValue(), LD->getSrcValueOffset(),
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LD->isVolatile(), LD->isNonTemporal(), 0);
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return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
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LD->getSrcValue(), LD->getSrcValueOffset(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->getAlignment());
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} else if (NumElems == 4 && LastLoadedElt == 1) {
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
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SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
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}
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return SDValue();
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}
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}
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/// PerformShuffleCombine - Detect vector gather/scatter index generation
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/// PerformShuffleCombine - Detect vector gather/scatter index generation
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9
test/CodeGen/X86/vec_insert-9.ll
Normal file
9
test/CodeGen/X86/vec_insert-9.ll
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@ -0,0 +1,9 @@
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; RUN: llc < %s -march=x86 -mattr=+sse41 > %t
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; RUN: grep pinsrd %t | count 2
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define <4 x i32> @var_insert2(<4 x i32> %x, i32 %val, i32 %idx) nounwind {
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entry:
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%tmp3 = insertelement <4 x i32> undef, i32 %val, i32 0 ; <<4 x i32>> [#uses=1]
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%tmp4 = insertelement <4 x i32> %tmp3, i32 %idx, i32 3 ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %tmp4
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 | grep punpckl | count 7
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; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7
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define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
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define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
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%tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
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%tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]
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@ -1,5 +1,6 @@
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; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
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; RUN: llc < %s -march=x86 -mcpu=core2 -o %t
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; RUN: grep shufp %t | count 1
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; RUN: grep movq %t | count 1
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; RUN: grep pshufd %t | count 1
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; RUN: grep movupd %t | count 1
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; RUN: grep movupd %t | count 1
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; RUN: grep pshufhw %t | count 1
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; RUN: grep pshufhw %t | count 1
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