mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 02:55:35 +00:00
Move all of the x86 subtarget initialized variables down into the x86 subtarget
from the x86 target machine. Should be no functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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405ed284b7
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fdea941583
@ -21606,3 +21606,7 @@ int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
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return AM.Scale != 0;
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return AM.Scale != 0;
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return -1;
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return -1;
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}
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}
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bool X86TargetLowering::isTargetFTOL() const {
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return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
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}
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@ -15,13 +15,13 @@
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#ifndef X86ISELLOWERING_H
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetOptions.h"
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namespace llvm {
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namespace llvm {
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class X86Subtarget;
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class X86TargetMachine;
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class X86TargetMachine;
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namespace X86ISD {
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namespace X86ISD {
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@ -766,9 +766,7 @@ namespace llvm {
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/// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
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/// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
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/// for fptoui.
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/// for fptoui.
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bool isTargetFTOL() const {
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bool isTargetFTOL() const;
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return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
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}
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/// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
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/// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
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/// used for fptoui to the given type.
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/// used for fptoui to the given type.
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@ -23,7 +23,7 @@ namespace llvm {
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class X86JITInfo : public TargetJITInfo {
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class X86JITInfo : public TargetJITInfo {
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uintptr_t PICBase;
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uintptr_t PICBase;
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char* TLSOffset;
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char *TLSOffset;
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bool useSSE;
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bool useSSE;
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public:
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public:
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explicit X86JITInfo(bool UseSSE);
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explicit X86JITInfo(bool UseSSE);
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@ -297,8 +297,47 @@ void X86Subtarget::initializeEnvironment() {
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MaxInlineSizeThreshold = 128;
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MaxInlineSizeThreshold = 128;
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}
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}
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static std::string computeDataLayout(const X86Subtarget &ST) {
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// X86 is little endian
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std::string Ret = "e";
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Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
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// X86 and x32 have 32 bit pointers.
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if (ST.isTarget64BitILP32() || !ST.is64Bit())
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Ret += "-p:32:32";
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// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
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if (ST.is64Bit() || ST.isOSWindows() || ST.isTargetNaCl())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// Some ABIs align long double to 128 bits, others to 32.
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if (ST.isTargetNaCl())
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; // No f80
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else if (ST.is64Bit() || ST.isTargetDarwin())
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Ret += "-f80:128";
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else
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Ret += "-f80:32";
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// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
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if (ST.is64Bit())
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Ret += "-n8:16:32:64";
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else
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Ret += "-n8:16:32";
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// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
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if (!ST.is64Bit() && ST.isOSWindows())
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Ret += "-S32";
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else
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Ret += "-S128";
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return Ret;
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}
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X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, unsigned StackAlignOverride)
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const std::string &FS, X86TargetMachine &TM,
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unsigned StackAlignOverride)
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: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
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: X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
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PICStyle(PICStyles::None), TargetTriple(TT),
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PICStyle(PICStyles::None), TargetTriple(TT),
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StackAlignOverride(StackAlignOverride),
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StackAlignOverride(StackAlignOverride),
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@ -306,9 +345,24 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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In32BitMode(TargetTriple.getArch() == Triple::x86 &&
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In32BitMode(TargetTriple.getArch() == Triple::x86 &&
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TargetTriple.getEnvironment() != Triple::CODE16),
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TargetTriple.getEnvironment() != Triple::CODE16),
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In16BitMode(TargetTriple.getArch() == Triple::x86 &&
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In16BitMode(TargetTriple.getArch() == Triple::x86 &&
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TargetTriple.getEnvironment() == Triple::CODE16) {
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TargetTriple.getEnvironment() == Triple::CODE16),
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DL(computeDataLayout(*this)), TSInfo(DL) {
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initializeEnvironment();
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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resetSubtargetFeatures(CPU, FS);
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// Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
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// X86TargetLowering needs.
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InstrInfo = new X86InstrInfo(TM);
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TLInfo = new X86TargetLowering(TM);
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FrameLowering = new X86FrameLowering(TargetFrameLowering::StackGrowsDown,
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getStackAlignment(),
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is64Bit() ? -8 : -4);
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JITInfo = new X86JITInfo(hasSSE1());
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}
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X86Subtarget::~X86Subtarget() {
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delete TLInfo;
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delete InstrInfo;
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delete FrameLowering;
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}
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}
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bool
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bool
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@ -14,6 +14,11 @@
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#ifndef X86SUBTARGET_H
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#ifndef X86SUBTARGET_H
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#define X86SUBTARGET_H
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#define X86SUBTARGET_H
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#include "X86FrameLowering.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86JITInfo.h"
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#include "X86SelectionDAGInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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@ -40,6 +45,7 @@ enum Style {
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}
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}
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class X86Subtarget final : public X86GenSubtargetInfo {
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class X86Subtarget final : public X86GenSubtargetInfo {
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protected:
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protected:
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enum X86SSEEnum {
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enum X86SSEEnum {
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NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
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NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
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@ -220,13 +226,29 @@ private:
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/// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
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/// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
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bool In16BitMode;
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bool In16BitMode;
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// Calculates type size & alignment
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const DataLayout DL;
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X86SelectionDAGInfo TSInfo;
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X86TargetLowering *TLInfo;
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X86InstrInfo *InstrInfo;
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X86FrameLowering *FrameLowering;
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X86JITInfo *JITInfo;
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public:
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public:
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/// This constructor initializes the data members to match that
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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/// of the specified triple.
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///
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///
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X86Subtarget(const std::string &TT, const std::string &CPU,
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X86Subtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS,
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const std::string &FS, X86TargetMachine &TM,
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unsigned StackAlignOverride);
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unsigned StackAlignOverride);
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~X86Subtarget();
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const X86TargetLowering *getTargetLowering() const { return TLInfo; }
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const X86InstrInfo *getInstrInfo() const { return InstrInfo; }
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const DataLayout *getDataLayout() const { return &DL; }
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const X86FrameLowering *getFrameLowering() const { return FrameLowering; }
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const X86SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
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X86JITInfo *getJITInfo() { return JITInfo; }
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// getStackAlignment - Returns the minimum alignment known to hold of the
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/// stack frame on entry to the function and which must be maintained by every
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/// stack frame on entry to the function and which must be maintained by every
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@ -29,44 +29,6 @@ extern "C" void LLVMInitializeX86Target() {
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void X86TargetMachine::anchor() { }
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void X86TargetMachine::anchor() { }
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static std::string computeDataLayout(const X86Subtarget &ST) {
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// X86 is little endian
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std::string Ret = "e";
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Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
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// X86 and x32 have 32 bit pointers.
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if (ST.isTarget64BitILP32() || !ST.is64Bit())
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Ret += "-p:32:32";
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// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
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if (ST.is64Bit() || ST.isOSWindows() || ST.isTargetNaCl())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// Some ABIs align long double to 128 bits, others to 32.
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if (ST.isTargetNaCl())
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; // No f80
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else if (ST.is64Bit() || ST.isTargetDarwin())
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Ret += "-f80:128";
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else
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Ret += "-f80:32";
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// The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
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if (ST.is64Bit())
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Ret += "-n8:16:32:64";
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else
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Ret += "-n8:16:32";
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// The stack is aligned to 32 bits on some ABIs and 128 bits on others.
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if (!ST.is64Bit() && ST.isOSWindows())
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Ret += "-S32";
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else
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Ret += "-S128";
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return Ret;
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}
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/// X86TargetMachine ctor - Create an X86 target.
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/// X86TargetMachine ctor - Create an X86 target.
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///
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///
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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@ -74,12 +36,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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Reloc::Model RM, CodeModel::Model CM,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
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Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
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FrameLowering(TargetFrameLowering::StackGrowsDown,
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Subtarget.getStackAlignment(),
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Subtarget.is64Bit() ? -8 : -4),
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DL(computeDataLayout(*getSubtargetImpl())), InstrInfo(*this),
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TLInfo(*this), TSInfo(DL), JITInfo(Subtarget.hasSSE1()) {
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// Determine the PICStyle based on the target selected.
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// Determine the PICStyle based on the target selected.
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if (getRelocationModel() == Reloc::Static) {
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if (getRelocationModel() == Reloc::Static) {
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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#include "X86ISelLowering.h"
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#include "X86ISelLowering.h"
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#include "X86InstrInfo.h"
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#include "X86InstrInfo.h"
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#include "X86JITInfo.h"
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#include "X86JITInfo.h"
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#include "X86SelectionDAGInfo.h"
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#include "X86Subtarget.h"
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#include "X86Subtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetMachine.h"
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@ -30,12 +29,6 @@ class StringRef;
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class X86TargetMachine final : public LLVMTargetMachine {
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class X86TargetMachine final : public LLVMTargetMachine {
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virtual void anchor();
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virtual void anchor();
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X86Subtarget Subtarget;
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X86Subtarget Subtarget;
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X86FrameLowering FrameLowering;
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const DataLayout DL; // Calculates type size & alignment
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X86InstrInfo InstrInfo;
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X86TargetLowering TLInfo;
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X86SelectionDAGInfo TSInfo;
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X86JITInfo JITInfo;
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public:
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public:
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X86TargetMachine(const Target &T, StringRef TT,
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X86TargetMachine(const Target &T, StringRef TT,
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Reloc::Model RM, CodeModel::Model CM,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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CodeGenOpt::Level OL);
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const DataLayout *getDataLayout() const override { return &DL; }
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const DataLayout *getDataLayout() const override {
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return getSubtargetImpl()->getDataLayout();
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}
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const X86InstrInfo *getInstrInfo() const override {
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const X86InstrInfo *getInstrInfo() const override {
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return &InstrInfo;
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return getSubtargetImpl()->getInstrInfo();
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}
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}
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const TargetFrameLowering *getFrameLowering() const override {
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const TargetFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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return getSubtargetImpl()->getFrameLowering();
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}
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X86JITInfo *getJITInfo() override {
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return &JITInfo;
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}
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}
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X86JITInfo *getJITInfo() override { return Subtarget.getJITInfo(); }
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const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
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const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
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const X86TargetLowering *getTargetLowering() const override {
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const X86TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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return getSubtargetImpl()->getTargetLowering();
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}
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}
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const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
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const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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return getSubtargetImpl()->getSelectionDAGInfo();
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}
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}
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const X86RegisterInfo *getRegisterInfo() const override {
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const X86RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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return &getInstrInfo()->getRegisterInfo();
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