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Cleanup TableGen subtarget emitter.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-10-03 23:06:25 +00:00
parent d494a3bfc5
commit fe05d98c25
2 changed files with 7 additions and 6 deletions
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5
utils/TableGen/CodeGenSchedule.cpp
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@ -72,9 +72,6 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
// Infer new SchedClasses from SchedVariant. // Infer new SchedClasses from SchedVariant.
inferSchedClasses(); inferSchedClasses();
DEBUG(for (unsigned i = 0; i < SchedClasses.size(); ++i)
SchedClasses[i].dump(this));
// Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and // Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
// ProcResourceDefs. // ProcResourceDefs.
collectProcResources(); collectProcResources();
@ -475,7 +472,7 @@ void CodeGenSchedModels::collectSchedClasses() {
RWI != RWE; ++RWI) { RWI != RWE; ++RWI) {
const CodeGenProcModel &ProcModel = const CodeGenProcModel &ProcModel =
getProcModel((*RWI)->getValueAsDef("SchedModel")); getProcModel((*RWI)->getValueAsDef("SchedModel"));
dbgs() << "InstrRW on " << ProcModel.ModelName << " for " << InstName; dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
IdxVec Writes; IdxVec Writes;
IdxVec Reads; IdxVec Reads;
findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"), findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),

8
utils/TableGen/SubtargetEmitter.cpp
View File

@ -11,6 +11,8 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#define DEBUG_TYPE "subtarget-emitter"
#include "CodeGenTarget.h" #include "CodeGenTarget.h"
#include "CodeGenSchedule.h" #include "CodeGenSchedule.h"
#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringExtras.h"
@ -769,6 +771,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(), for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) { SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
DEBUG(SCI->dump(&SchedModels));
SCTab.resize(SCTab.size() + 1); SCTab.resize(SCTab.size() + 1);
MCSchedClassDesc &SCDesc = SCTab.back(); MCSchedClassDesc &SCDesc = SCTab.back();
// SCDesc.Name is guarded by NDEBUG // SCDesc.Name is guarded by NDEBUG
@ -817,8 +821,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
} }
} }
else if (!SCI->InstRWs.empty()) { else if (!SCI->InstRWs.empty()) {
assert(SCI->Writes.empty() && SCI->Reads.empty() && // This class may have a default ReadWrite list which can be overriden by
"InstRW class should not have its own ReadWrites"); // InstRW definitions.
Record *RWDef = 0; Record *RWDef = 0;
for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end(); for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
RWI != RWE; ++RWI) { RWI != RWE; ++RWI) {