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Finally implement correct ordered comparisons for PPC, even though
the code generated is not wonderful. This turns a miscompilation into a code quality bug (noted in the ppc readme). This fixes PR642, which is over 2 years old (!). Nate, please review this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45742 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -624,29 +624,34 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
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/// getCRIdxForSetCC - Return the index of the condition register field
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/// associated with the SetCC condition, and whether or not the field is
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/// treated as inverted. That is, lt = 0; ge = 0 inverted.
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static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
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///
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/// If this returns with Other != -1, then the returned comparison is an or of
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/// two simpler comparisons. In this case, Invert is guaranteed to be false.
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static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
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Invert = false;
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Other = -1;
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switch (CC) {
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default: assert(0 && "Unknown condition!"); abort();
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case ISD::SETOLT: // FIXME: This is incorrect see PR642.
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case ISD::SETULT:
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case ISD::SETLT: Inv = false; return 0;
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case ISD::SETOGE: // FIXME: This is incorrect see PR642.
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case ISD::SETOLT:
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case ISD::SETLT: return 0; // Bit #0 = SETOLT
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case ISD::SETOGT:
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case ISD::SETGT: return 1; // Bit #1 = SETOGT
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case ISD::SETOEQ:
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case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
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case ISD::SETUO: return 3; // Bit #3 = SETUO
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case ISD::SETUGE:
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case ISD::SETGE: Inv = true; return 0;
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case ISD::SETOGT: // FIXME: This is incorrect see PR642.
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case ISD::SETUGT:
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case ISD::SETGT: Inv = false; return 1;
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case ISD::SETOLE: // FIXME: This is incorrect see PR642.
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case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
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case ISD::SETULE:
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case ISD::SETLE: Inv = true; return 1;
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case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
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case ISD::SETUEQ:
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case ISD::SETEQ: Inv = false; return 2;
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case ISD::SETONE: // FIXME: This is incorrect see PR642.
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case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
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case ISD::SETUNE:
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case ISD::SETNE: Inv = true; return 2;
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case ISD::SETO: Inv = true; return 3;
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case ISD::SETUO: Inv = false; return 3;
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case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
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case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
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case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO
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case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO
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case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO
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case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ
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case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ
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case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT
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}
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return 0;
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}
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@ -726,7 +731,8 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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}
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bool Inv;
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unsigned Idx = getCRIdxForSetCC(CC, Inv);
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int OtherCondIdx;
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unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
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SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
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SDOperand IntCR;
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@ -737,7 +743,7 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
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InFlag).getValue(1);
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if (PPCSubTarget.isGigaProcessor())
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if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
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IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
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CCReg), 0);
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else
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@ -745,13 +751,26 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
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getI32Imm(31), getI32Imm(31) };
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if (!Inv) {
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if (OtherCondIdx == -1 && !Inv)
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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} else {
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SDOperand Tmp =
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SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
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// Get the specified bit.
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SDOperand Tmp =
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SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
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if (Inv) {
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assert(OtherCondIdx == -1 && "Can't have split plus negation");
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return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
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}
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// Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
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// We already got the bit for the first part of the comparison (e.g. SETULE).
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// Get the other bit of the comparison.
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Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
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SDOperand OtherCond =
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SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
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return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
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}
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@ -706,3 +706,32 @@ __Z11no_overflowjj:
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//===---------------------------------------------------------------------===//
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We compile some FP comparisons into an mfcr with two rlwinms and an or. For
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example:
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#include <math.h>
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int test(double x, double y) { return islessequal(x, y);}
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int test2(double x, double y) { return islessgreater(x, y);}
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int test3(double x, double y) { return !islessequal(x, y);}
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Compiles into (all three are similar, but the bits differ):
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_test:
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fcmpu cr7, f1, f2
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mfcr r2
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rlwinm r3, r2, 29, 31, 31
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rlwinm r2, r2, 31, 31, 31
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or r3, r2, r3
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blr
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GCC compiles this into:
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_test:
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fcmpu cr7,f1,f2
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cror 30,28,30
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mfcr r3
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rlwinm r3,r3,31,1
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blr
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which is more efficient and can use mfocr. See PR642 for some more context.
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//===---------------------------------------------------------------------===//
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27
test/CodeGen/PowerPC/compare-fcmp-ord.ll
Normal file
27
test/CodeGen/PowerPC/compare-fcmp-ord.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: llvm-as < %s | llc -march=ppc32 | grep or | count 3
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; This should produce one 'or' or 'cror' instruction per function.
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i686-apple-darwin8"
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define i32 @test(double %x, double %y) nounwind {
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entry:
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%tmp3 = fcmp ole double %x, %y ; <i1> [#uses=1]
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%tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
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ret i32 %tmp345
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}
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define i32 @test2(double %x, double %y) nounwind {
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entry:
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%tmp3 = fcmp one double %x, %y ; <i1> [#uses=1]
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%tmp345 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
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ret i32 %tmp345
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}
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define i32 @test3(double %x, double %y) nounwind {
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entry:
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%tmp3 = fcmp ugt double %x, %y ; <i1> [#uses=1]
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%tmp34 = zext i1 %tmp3 to i32 ; <i32> [#uses=1]
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ret i32 %tmp34
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}
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