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Move DAGSize to SelectionDAGISel; it's used in tablegen'd isel code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29547 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-08-07 22:16:08 +00:00
parent 99157a00a6
commit fe8dc2e2c8
1 changed files with 7 additions and 2 deletions
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9
include/llvm/CodeGen/SelectionDAGISel.h
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@ -17,10 +17,10 @@
#include "llvm/Pass.h"
#include "llvm/Constant.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
namespace llvm {
class SelectionDAG;
class SelectionDAGLowering;
class SDOperand;
class SSARegMap;
@ -39,8 +39,10 @@ public:
SSARegMap *RegMap;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
std::vector<SDNode*> TopOrder;
unsigned DAGSize;
SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
TargetLowering &getTargetLowering() { return TLI; }
@ -52,6 +54,9 @@ public:
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
virtual void SelectRootInit() {
DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
}
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint code. If this does