mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-18 12:29:27 +00:00
Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
fe67ca209f
commit
feab2f837c
@ -41,7 +41,46 @@ namespace {
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static const int64_t IMM_LOW = -32768;
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static const int64_t IMM_HIGH = 32767;
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static const int64_t IMM_MULT = 65536;
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static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
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static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
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static int64_t get_ldah16(int64_t x) {
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int64_t y = x / IMM_MULT;
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if (x % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static int64_t get_lda16(int64_t x) {
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return x - get_ldah16(x) * IMM_MULT;
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}
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static uint64_t get_zapImm(uint64_t x) {
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unsigned int build = 0;
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for(int i = 0; i < 8; ++i)
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{
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if ((x & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((x & 0x00FF) != 0)
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{ build = 0; break; }
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x >>= 8;
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}
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return x;
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}
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static bool isFPZ(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
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}
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static bool isFPZn(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->isExactlyValue(-0.0));
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}
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static bool isFPZp(SDOperand N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->isExactlyValue(+0.0));
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}
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public:
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AlphaDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
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@ -154,46 +193,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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CodeGenMap[Op.getValue(1)] = Result.getValue(1);
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return SDOperand(Result.Val, Op.ResNo);
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}
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case ISD::BRCOND: {
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if (N->getOperand(1).getOpcode() == ISD::SETCC &&
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MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand CC1 = Select(N->getOperand(1).getOperand(0));
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SDOperand CC2 = Select(N->getOperand(1).getOperand(1));
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ISD::CondCode cCode= cast<CondCodeSDNode>(N->getOperand(1).getOperand(2))->get();
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bool rev = false;
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bool isNE = false;
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unsigned Opc = Alpha::WTF;
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switch(cCode) {
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default: N->dump(); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
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case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
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};
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SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
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rev?CC2:CC1,
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rev?CC1:CC2);
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
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if(isNE)
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return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp,
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CurDAG->getBasicBlock(Dest), Chain);
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else
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return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp,
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CurDAG->getBasicBlock(Dest), Chain);
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}
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand CC = Select(N->getOperand(1));
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
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return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC,
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CurDAG->getBasicBlock(Dest), Chain);
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}
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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@ -248,8 +247,8 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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val >= IMM_LOW + IMM_LOW * IMM_MULT)
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break; //(LDAH (LDA))
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if ((uval >> 32) == 0 && //empty upper bits
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val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
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val32 >= IMM_LOW + IMM_LOW * IMM_MULT)
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val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
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// val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
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break; //(zext (LDAH (LDA)))
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//Else use the constant pool
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MachineConstantPool *CP = BB->getParent()->getConstantPool();
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@ -107,10 +107,23 @@ class BFormD<bits<6> opcode, string asmstr, list<dag> pattern>
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class BFormDG<bits<6> opcode, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops GPRC:$RA, target:$DISP), asmstr> {
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let Pattern = pattern;
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class FBForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops F8RC:$RA, s21imm:$DISP), asmstr> {
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class FBForm<bits<6> opcode, string asmstr, list<dag> pattern>
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: InstAlpha<opcode, (ops F8RC:$RA, target:$DISP), asmstr> {
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let Pattern = pattern;
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bits<5> Ra;
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bits<21> disp;
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@ -34,72 +34,56 @@ def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq,[SDNPHasChain]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq,[SDNPHasChain]>;
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def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
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def fpimm : SDNode<"ISD::ConstantFP" , SDTFPLeaf , [], "ConstantFPSDNode">;
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//********************
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//Paterns for matching
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//********************
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def invX : SDNodeXForm<imm, [{
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def invX : SDNodeXForm<imm, [{ //invert
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return getI64Imm(~N->getValue());
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}]>;
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def immUExt8 : PatLeaf<(imm), [{
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// immUExt8 predicate - True if the immediate fits in a 8-bit zero extended
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// field. Used by instructions like 'addi'.
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return (uint64_t)N->getValue() == (uint8_t)N->getValue();
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def negX : SDNodeXForm<imm, [{ //negate
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return getI64Imm(~N->getValue() + 1);
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}]>;
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def immUExt8inv : PatLeaf<(imm), [{
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// immUExt8inv predicate - True if the inverted immediate fits in a 8-bit zero extended
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// field. Used by instructions like 'ornoti'.
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return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
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}], invX>;
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
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// field. Used by instructions like 'lda'.
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return (int64_t)N->getValue() == (int16_t)N->getValue();
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}]>;
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def SExtInt : SDNodeXForm<imm, [{
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def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
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return getI64Imm(((int64_t)N->getValue() << 32) >> 32);
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}]>;
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def immSExt16int : PatLeaf<(imm), [{
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// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
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// field. Used by instructions like 'lda'.
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int64_t val = (int64_t)N->getValue();
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uint32_t uval32 = (uint32_t)val;
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int32_t val32 = (int32_t)val;
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return (int64_t)uval32 == val && val32 == (int16_t)val32;
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}], SExtInt>;
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def iZAPX : SDNodeXForm<imm, [{
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// Transformation function: get the imm to ZAPi
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uint64_t UImm = (uint64_t)N->getValue();
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unsigned int build = 0;
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for(int i = 0; i < 8; ++i)
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{
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if ((UImm & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((UImm & 0x00FF) != 0)
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{ build = 0; break; }
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UImm >>= 8;
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}
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return getI64Imm(build);
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def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
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return getI64Imm(((int64_t)N->getValue() << 48) >> 48);
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}]>;
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def immZAP : PatLeaf<(imm), [{
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// immZAP predicate - True if the immediate fits is suitable for use in a
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// ZAP instruction
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uint64_t UImm = (uint64_t)N->getValue();
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unsigned int build = 0;
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for(int i = 0; i < 8; ++i)
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{
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if ((UImm & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((UImm & 0x00FF) != 0)
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{ build = 0; break; }
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UImm >>= 8;
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}
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def LL16 : SDNodeXForm<imm, [{ //lda part of constant
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return getI64Imm(get_lda16(N->getValue()));
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}]>;
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def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
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return getI64Imm(get_ldah16(N->getValue()));
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}]>;
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def iZAPX : SDNodeXForm<imm, [{ // get imm to ZAPi
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return getI64Imm(get_zapImm((uint64_t)N->getValue()));
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}]>;
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def immUExt8 : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
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return (uint64_t)N->getValue() == (uint8_t)N->getValue();
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}]>;
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def immUExt8inv : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
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return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
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}], invX>;
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def immUExt8neg : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
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return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1);
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}], negX>;
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def immSExt16 : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
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return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue();
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}]>;
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def immSExt16int : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
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return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32;
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}], SExt16>;
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def immZAP : PatLeaf<(imm), [{ //imm is good for zapi
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uint64_t build = get_zapImm((uint64_t)N->getValue());
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return build != 0;
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}], iZAPX>;
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def immFPZ : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
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return true;
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}]>;
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def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
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def add4 : PatFrag<(ops node:$op1, node:$op2),
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@ -111,11 +95,8 @@ def add8 : PatFrag<(ops node:$op1, node:$op2),
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def sub8 : PatFrag<(ops node:$op1, node:$op2),
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(sub (shl node:$op1, 3), node:$op2)>;
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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//Pseudo ops for selection
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def PHI : PseudoInstAlpha<(ops variable_ops), "#phi", []>;
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@ -127,6 +108,7 @@ def IDEF_F64 : PseudoInstAlpha<(ops F8RC:$RA), "#idef $RA",
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[(set F8RC:$RA, (undef))]>;
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def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", []>;
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let isLoad = 1, hasCtrlDep = 1 in {
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def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt",
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[(callseq_start imm:$amt)]>;
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@ -138,12 +120,7 @@ def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[]>;
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def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
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"LSMARKER$$$i$$$j$$$k$$$m:\n",[]>;
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//*****************
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//These are shortcuts, the assembler expands them
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//*****************
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//AT = R28
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//T0-T7 = R1 - R8
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//T8-T11 = R22-R25
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//An even better improvement on the Int = SetCC(FP): SelectCC!
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//These are evil because they hide control flow in a MBB
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@ -322,11 +299,11 @@ def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC",
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def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC",
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[(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))]>;
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def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC",
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[(set GPRC:$RC, (intop (sub8 GPRC:$RA, immUExt8:$L)))]>;
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[(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))]>;
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def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
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[(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))]>;
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def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
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[(set GPRC:$RC, (sub8 GPRC:$RA, immUExt8:$L))]>;
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[(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))]>;
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def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC",
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[(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))]>;
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def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC",
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@ -346,11 +323,11 @@ def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC",
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def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
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[(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))]>;
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def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
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[(set GPRC:$RC, (intop (sub GPRC:$RA, immUExt8:$L)))]>;
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[(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))]>;
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def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
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[(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))]>;
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def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
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[(set GPRC:$RC, (sub GPRC:$RA, immUExt8:$L))]>;
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[(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))]>;
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def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
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[(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))]>;
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def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC",
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@ -449,10 +426,6 @@ let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
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def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
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let Ra = 31 in
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def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
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let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
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def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
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[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))]>;
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@ -594,24 +567,6 @@ def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
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def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
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(LDQl texternalsym:$ext, GPRC:$RB)>;
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//Branches, int
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def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
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def BGE : BForm<0x3E, "bge $RA,$DISP">; //Branch if >= zero
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def BGT : BForm<0x3F, "bgt $RA,$DISP">; //Branch if > zero
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def BLBC : BForm<0x38, "blbc $RA,$DISP">; //Branch if low bit clear
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def BLBS : BForm<0x3C, "blbs $RA,$DISP">; //Branch if low bit set
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def BLE : BForm<0x3B, "ble $RA,$DISP">; //Branch if <= zero
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def BLT : BForm<0x3A, "blt $RA,$DISP">; //Branch if < zero
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def BNE : BForm<0x3D, "bne $RA,$DISP">; //Branch if != zero
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//Branches, float
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def FBEQ : FBForm<0x31, "fbeq $RA,$DISP">; //Floating branch if = zero
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def FBGE : FBForm<0x36, "fbge $RA,$DISP">; //Floating branch if >= zero
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def FBGT : FBForm<0x37, "fbgt $RA,$DISP">; //Floating branch if > zero
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def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero
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def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
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def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
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def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
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//Basic Floating point ops
|
||||
@ -747,6 +702,63 @@ let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
|
||||
def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
|
||||
[(set F4RC:$RC, (fround F8RC:$RB))]>;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
//Branching
|
||||
/////////////////////////////////////////////////////////
|
||||
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
|
||||
let Ra = 31 in
|
||||
def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)]>;
|
||||
|
||||
//Branches, int
|
||||
def BEQ : BFormDG<0x39, "beq $RA,$DISP",
|
||||
[(brcond (seteq GPRC:$RA, 0), bb:$DISP)]>;
|
||||
def BGE : BFormDG<0x3E, "bge $RA,$DISP",
|
||||
[(brcond (setge GPRC:$RA, 0), bb:$DISP)]>;
|
||||
def BGT : BFormDG<0x3F, "bgt $RA,$DISP",
|
||||
[(brcond (setgt GPRC:$RA, 0), bb:$DISP)]>;
|
||||
def BLBC : BFormDG<0x38, "blbc $RA,$DISP", []>; //TODO: Low bit clear
|
||||
def BLBS : BFormDG<0x3C, "blbs $RA,$DISP",
|
||||
[(brcond (seteq GPRC:$RA, 1), bb:$DISP)]>;
|
||||
def BLE : BFormDG<0x3B, "ble $RA,$DISP",
|
||||
[(brcond (setle GPRC:$RA, 0), bb:$DISP)]>;
|
||||
def BLT : BFormDG<0x3A, "blt $RA,$DISP",
|
||||
[(brcond (setlt GPRC:$RA, 0), bb:$DISP)]>;
|
||||
def BNE : BFormDG<0x3D, "bne $RA,$DISP",
|
||||
[(brcond (setne GPRC:$RA, 0), bb:$DISP)]>;
|
||||
|
||||
//Branches, float
|
||||
def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
|
||||
[(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
def FBGE : FBForm<0x36, "fbge $RA,$DISP",
|
||||
[(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
def FBGT : FBForm<0x37, "fbgt $RA,$DISP",
|
||||
[(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
def FBLE : FBForm<0x33, "fble $RA,$DISP",
|
||||
[(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
def FBLT : FBForm<0x32, "fblt $RA,$DISP",
|
||||
[(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
def FBNE : FBForm<0x35, "fbne $RA,$DISP",
|
||||
[(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)]>;
|
||||
}
|
||||
|
||||
def : Pat<(brcond (and GPRC:$RA, 1), bb:$DISP), (BLBS GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>;
|
||||
def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
|
||||
def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP),
|
||||
(FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
|
||||
|
||||
//End Branches
|
||||
|
||||
//S_floating : IEEE Single
|
||||
//T_floating : IEEE Double
|
||||
|
||||
@ -794,34 +806,16 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
|
||||
def immConst2Part : PatLeaf<(imm), [{
|
||||
//true if imm fits in a LDAH LDA pair
|
||||
int64_t val = (int64_t)N->getValue();
|
||||
return (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &
|
||||
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT);
|
||||
return (val <= IMM_FULLHIGH && val >= IMM_FULLLOW);
|
||||
}]>;
|
||||
def immConst2PartInt : PatLeaf<(imm), [{
|
||||
//true if imm fits in a LDAH LDA pair with zeroext
|
||||
uint64_t uval = N->getValue();
|
||||
int32_t val32 = (int32_t)uval;
|
||||
return ((uval >> 32) == 0 && //empty upper bits
|
||||
val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
|
||||
val32 >= IMM_LOW + IMM_LOW * IMM_MULT);
|
||||
}], SExtInt>;
|
||||
|
||||
//TODO: factor this out
|
||||
def LL16 : SDNodeXForm<imm, [{
|
||||
int64_t l = N->getValue();
|
||||
int64_t y = l / IMM_MULT;
|
||||
if (l % IMM_MULT > IMM_HIGH)
|
||||
++y;
|
||||
return getI64Imm(l - y * IMM_MULT);
|
||||
}]>;
|
||||
//TODO: factor this out
|
||||
def LH16 : SDNodeXForm<imm, [{
|
||||
int64_t l = N->getValue();
|
||||
int64_t y = l / IMM_MULT;
|
||||
if (l % IMM_MULT > IMM_HIGH)
|
||||
++y;
|
||||
return getI64Imm(y);
|
||||
}]>;
|
||||
val32 <= IMM_FULLHIGH);
|
||||
// val32 >= IMM_FULLLOW + IMM_LOW * IMM_MULT); //Always True
|
||||
}], SExt32>;
|
||||
|
||||
def : Pat<(i64 immConst2Part:$imm),
|
||||
(LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>;
|
||||
@ -830,10 +824,10 @@ def : Pat<(i64 immSExt16:$imm),
|
||||
(LDA immSExt16:$imm, R31)>;
|
||||
|
||||
def : Pat<(i64 immSExt16int:$imm),
|
||||
(ZAPNOTi (LDA (SExtInt immSExt16int:$imm), R31), 15)>;
|
||||
(ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15)>;
|
||||
def : Pat<(i64 immConst2PartInt:$imm),
|
||||
(ZAPNOTi (LDA (LL16 (SExtInt immConst2PartInt:$imm)),
|
||||
(LDAH (LH16 (SExtInt immConst2PartInt:$imm)), R31)), 15)>;
|
||||
(ZAPNOTi (LDA (LL16 (SExt16 immConst2PartInt:$imm)),
|
||||
(LDAH (LH16 (SExt16 immConst2PartInt:$imm)), R31)), 15)>;
|
||||
|
||||
|
||||
//TODO: I want to just define these like this!
|
||||
|
||||
Loading…
Reference in New Issue
Block a user