From feac09801b5c03412d452e685570baff6eb84c88 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 21 Dec 2010 22:27:44 +0000 Subject: [PATCH] In DelayForLiveRegsBottomUp, handle instructions that read and write the same physical register. Simplifies the fix from the previous checkin r122211. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122370 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SelectionDAG/ScheduleDAGRRList.cpp | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 92341324047..a925a79cc69 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -660,9 +660,12 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector &LRegs) { SmallSet RegAdded; // If this node would clobber any "live" register, then it's not ready. + // + // If SU is the currently live definition of the same register that it uses, + // then we are free to schedule it. for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { - if (I->isAssignedRegDep()) + if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU) CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs, RegAdded, LRegs, TRI); } @@ -703,20 +706,6 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector &LRegs) { CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); } - - // Okay, we now know all of the live registers that are defined by an - // immediate predecessor. It is ok to kill these registers if we are also - // using it. - for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); - I != E; ++I) { - if (I->isAssignedRegDep() && - LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { - unsigned Reg = I->getReg(); - if (RegAdded.erase(Reg)) - LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg)); - } - } - return !LRegs.empty(); }