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For instructions in a delay slot of another instruction,

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we no longer need to find the live-before set of the delayed
branch since that set is now included the live-before/after
set of the instructions in each delay slot.  Just assert that instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7796 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2003-08-12 22:22:24 +00:00
parent 88d962aa58
commit feb3298fca
2 changed files with 32 additions and 24 deletions
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28
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
#include "Support/SetOperations.h"
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
@ -747,18 +748,21 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
// If this instr. is in the delay slot of a branch or return, use the live
// var set before that branch or return -- we don't want to trample those!
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
#ifndef NDEBUG
// If this instr. is in the delay slot of a branch or return, we need to
// include all live variables before that branch or return -- we don't want to
// trample those! Verify that the set is included in the LV set before MInst.
//
MachineInstr *LiveBeforeThisMI = MInst;
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode())) {
assert(DS == 1 && "Only checking immediate pred. for delay slots!");
LiveBeforeThisMI = PredMI;
}
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
"live-var set of each delay slot instruction!");
}
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(LiveBeforeThisMI,BB);
#endif
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
@ -1204,14 +1208,14 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
if (DEBUG_RA) {
// "added after" instructions of the original instr
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
if (DEBUG_RA && OrigAft.size() > 0) {
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
// "added after" instructions of the original instr
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;

28
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Type.h"
#include "llvm/iOther.h"
#include "Support/STLExtras.h"
#include "Support/SetOperations.h"
#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
@ -747,18 +748,21 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
RegClass *RC = LR->getRegClass();
// Get the live-variable set to find registers free before this instr.
// If this instr. is in the delay slot of a branch or return, use the live
// var set before that branch or return -- we don't want to trample those!
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
#ifndef NDEBUG
// If this instr. is in the delay slot of a branch or return, we need to
// include all live variables before that branch or return -- we don't want to
// trample those! Verify that the set is included in the LV set before MInst.
//
MachineInstr *LiveBeforeThisMI = MInst;
if (MII != MBB.begin()) {
MachineInstr *PredMI = *(MII-1);
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode())) {
assert(DS == 1 && "Only checking immediate pred. for delay slots!");
LiveBeforeThisMI = PredMI;
}
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
"live-var set of each delay slot instruction!");
}
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(LiveBeforeThisMI,BB);
#endif
MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
@ -1204,14 +1208,14 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI)
{
if (DEBUG_RA) {
// "added after" instructions of the original instr
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
if (DEBUG_RA && OrigAft.size() > 0) {
cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
cerr << " to last delay slot instrn: " << *DelayedMI;
}
// "added after" instructions of the original instr
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
// "added after" instructions of the delayed instr
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;