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InstCombine: variations on 0xffffffff - x >= 4
The following transforms are valid if -C is a power of 2: (icmp ugt (xor X, C), ~C) -> (icmp ult X, C) (icmp ult (xor X, C), -C) -> (icmp uge X, C) These are nice, they get rid of the xor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185915 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1126,6 +1126,18 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
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Builder->getInt(RHSV ^ NotSignBit));
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}
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}
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// (icmp ugt (xor X, C), ~C) -> (icmp ult X, C)
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// iff -C is a power of 2
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if (ICI.getPredicate() == ICmpInst::ICMP_UGT &&
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XorCST->getValue() == ~RHSV && (RHSV + 1).isPowerOf2())
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return new ICmpInst(ICmpInst::ICMP_ULT, LHSI->getOperand(0), XorCST);
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// (icmp ult (xor X, C), -C) -> (icmp uge X, C)
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// iff -C is a power of 2
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if (ICI.getPredicate() == ICmpInst::ICMP_ULT &&
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XorCST->getValue() == -RHSV && RHSV.isPowerOf2())
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return new ICmpInst(ICmpInst::ICMP_UGE, LHSI->getOperand(0), XorCST);
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}
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break;
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case Instruction::And: // (icmp pred (and X, AndCST), RHS)
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@ -1181,3 +1181,21 @@ define i1 @icmp_and_X_-16_ne-16(i32 %X) {
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%cmp = icmp ne i32 %and, -16
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ret i1 %cmp
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}
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; CHECK: @icmp_sub_-1_X_ult_4
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; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -5
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; CHECK-NEXT: ret i1 [[CMP]]
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define i1 @icmp_sub_-1_X_ult_4(i32 %X) {
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%sub = sub i32 -1, %X
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%cmp = icmp ult i32 %sub, 4
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ret i1 %cmp
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}
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; CHECK: @icmp_sub_-1_X_uge_4
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; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %X, -4
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; CHECK-NEXT: ret i1 [[CMP]]
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define i1 @icmp_sub_-1_X_uge_4(i32 %X) {
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%sub = sub i32 -1, %X
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%cmp = icmp uge i32 %sub, 4
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ret i1 %cmp
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}
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