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[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.

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- Rename function.
- Pass iterator by value.
- Remove header include.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2013-04-11 19:07:14 +00:00
parent 59a8b5a8f0
commit fee62c167b
3 changed files with 12 additions and 13 deletions
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4
lib/Target/Mips/MipsCodeEmitter.cpp
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@@ -116,7 +116,7 @@ private:
int Offset) const; int Offset) const;
/// Expand pseudo instructions with accumulator register operands. /// Expand pseudo instructions with accumulator register operands.
void expandACCInstr(MachineBasicBlock::instr_iterator &MI, void expandACCInstr(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB, unsigned Opc) const; MachineBasicBlock &MBB, unsigned Opc) const;
/// \brief Expand pseudo instruction. Return true if MI was expanded. /// \brief Expand pseudo instruction. Return true if MI was expanded.
@@ -302,7 +302,7 @@ void MipsCodeEmitter::emitWord(unsigned Word) {
MCE.emitWordBE(Word); MCE.emitWordBE(Word);
} }
void MipsCodeEmitter::expandACCInstr(MachineBasicBlock::instr_iterator &MI, void MipsCodeEmitter::expandACCInstr(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
unsigned Opc) const { unsigned Opc) const {
// Expand "pseudomult $ac0, $t0, $t1" to "mult $t0, $t1". // Expand "pseudomult $ac0, $t0, $t1" to "mult $t0, $t1".

1
lib/Target/Mips/MipsISelDAGToDAG.cpp
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@@ -17,7 +17,6 @@
#include "MipsSEISelDAGToDAG.h" #include "MipsSEISelDAGToDAG.h"
#include "Mips.h" #include "Mips.h"
#include "MCTargetDesc/MipsBaseInfo.h" #include "MCTargetDesc/MipsBaseInfo.h"
#include "MipsAnalyzeImmediate.h"
#include "MipsMachineFunction.h" #include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h" #include "MipsRegisterInfo.h"
#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineConstantPool.h"

20
lib/Target/Mips/MipsISelLowering.cpp
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@@ -1918,7 +1918,7 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
return DAG.getMergeValues(Ops, 2, DL); return DAG.getMergeValues(Ops, 2, DL);
} }
static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
SDValue Chain, SDValue Src, unsigned Offset) { SDValue Chain, SDValue Src, unsigned Offset) {
SDValue Ptr = LD->getBasePtr(); SDValue Ptr = LD->getBasePtr();
EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
@@ -1958,15 +1958,15 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
// (set tmp, (ldl (add baseptr, 7), undef)) // (set tmp, (ldl (add baseptr, 7), undef))
// (set dst, (ldr baseptr, tmp)) // (set dst, (ldr baseptr, tmp))
if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
IsLittle ? 7 : 0); IsLittle ? 7 : 0);
return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
IsLittle ? 0 : 7); IsLittle ? 0 : 7);
} }
SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
IsLittle ? 3 : 0); IsLittle ? 3 : 0);
SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
IsLittle ? 0 : 3); IsLittle ? 0 : 3);
// Expand // Expand
@@ -1997,7 +1997,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues(Ops, 2, DL); return DAG.getMergeValues(Ops, 2, DL);
} }
static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
SDValue Chain, unsigned Offset) { SDValue Chain, unsigned Offset) {
SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
@@ -2034,9 +2034,9 @@ SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
// (swl val, (add baseptr, 3)) // (swl val, (add baseptr, 3))
// (swr val, baseptr) // (swr val, baseptr)
if ((VT == MVT::i32) || SD->isTruncatingStore()) { if ((VT == MVT::i32) || SD->isTruncatingStore()) {
SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain, SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
IsLittle ? 3 : 0); IsLittle ? 3 : 0);
return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
} }
assert(VT == MVT::i64); assert(VT == MVT::i64);
@@ -2046,8 +2046,8 @@ SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
// to // to
// (sdl val, (add baseptr, 7)) // (sdl val, (add baseptr, 7))
// (sdr val, baseptr) // (sdr val, baseptr)
SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
} }
static SDValue initAccumulator(SDValue In, DebugLoc DL, SelectionDAG &DAG) { static SDValue initAccumulator(SDValue In, DebugLoc DL, SelectionDAG &DAG) {