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Add support for trampolines on the XCore.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-02-02 14:57:41 +00:00
parent ae200c60c3
commit ff0c5014b2
5 changed files with 109 additions and 1 deletions
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3
lib/Target/XCore/XCoreCallingConv.td
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@ -24,6 +24,9 @@ def CC_XCore : CallingConv<[
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
// The 'nest' parameter, if any, is passed in R11.
CCIfNest<CCAssignToReg<[R11]>>,
// The first 4 integer arguments are passed in integer registers.
CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,

5
lib/Target/XCore/XCoreFrameLowering.cpp
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@ -100,6 +100,11 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
bool FP = hasFP(MF);
bool Nested = MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::Nest);
if (Nested) {
loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
}
// Work out frame sizes.
int FrameSize = MFI->getStackSize();

64
lib/Target/XCore/XCoreISelLowering.cpp
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@ -148,7 +148,10 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
// TRAMPOLINE is custom lowered.
setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
maxStoresPerMemmove = maxStoresPerMemmoveOptSize
= maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
@ -178,6 +181,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADD:
case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
default:
llvm_unreachable("unimplemented operand");
return SDValue();
@ -794,6 +798,64 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
RegInfo->getFrameRegister(MF), MVT::i32);
}
SDValue XCoreTargetLowering::
LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
// .align 4
// LDAPF_u10 r11, nest
// LDW_2rus r11, r11[0]
// STWSP_ru6 r11, sp[0]
// LDAPF_u10 r11, fptr
// LDW_2rus r11, r11[0]
// BAU_1r r11
// nest:
// .word nest
// fptr:
// .word fptr
SDValue OutChains[5];
SDValue Addr = Trmp;
DebugLoc dl = Op.getDebugLoc();
OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
Addr, MachinePointerInfo(TrmpAddr), false, false,
0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(4, MVT::i32));
OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
Addr, MachinePointerInfo(TrmpAddr, 4), false,
false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(8, MVT::i32));
OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
Addr, MachinePointerInfo(TrmpAddr, 8), false,
false, 0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(12, MVT::i32));
OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
MachinePointerInfo(TrmpAddr, 12), false, false,
0);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
DAG.getConstant(16, MVT::i32));
OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
MachinePointerInfo(TrmpAddr, 16), false, false,
0);
SDValue Ops[] =
{ Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5) };
return DAG.getMergeValues(Ops, 2, dl);
}
//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//

1
lib/Target/XCore/XCoreISelLowering.h
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@ -147,6 +147,7 @@ namespace llvm {
SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
// Inline asm support
std::vector<unsigned>

37
test/CodeGen/XCore/trampoline.ll Normal file
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@ -0,0 +1,37 @@
; RUN: llc < %s -march=xcore | FileCheck %s
%struct.FRAME.f = type { i32, i32 ()* }
define void @f() nounwind {
entry:
; CHECK: f:
; CHECK ldap r11, g.1101
; CHECK stw r11, sp[7]
%TRAMP.23 = alloca [20 x i8], align 2
%FRAME.0 = alloca %struct.FRAME.f, align 4
%TRAMP.23.sub = getelementptr inbounds [20 x i8]* %TRAMP.23, i32 0, i32 0
%FRAME.02 = bitcast %struct.FRAME.f* %FRAME.0 to i8*
%tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.23.sub, i8* bitcast (i32 (%struct.FRAME.f*)* @g.1101 to i8*), i8* %FRAME.02)
%0 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 1
%1 = bitcast i8* %tramp to i32 ()*
store i32 ()* %1, i32 ()** %0, align 4
%2 = getelementptr inbounds %struct.FRAME.f* %FRAME.0, i32 0, i32 0
store i32 1, i32* %2, align 4
call void @h(i32 ()* %1) nounwind
ret void
}
define internal i32 @g.1101(%struct.FRAME.f* nocapture nest %CHAIN.1) nounwind readonly {
entry:
; CHECK: g.1101:
; CHECK: ldw r11, sp[0]
; CHECK-NEXT: ldw r0, r11[0]
; CHECK-NEXT: retsp 0
%0 = getelementptr inbounds %struct.FRAME.f* %CHAIN.1, i32 0, i32 0
%1 = load i32* %0, align 4
ret i32 %1
}
declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind
declare void @h(i32 ()*)