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[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)

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The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modelled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Oliver Stannard
2014-10-01 09:02:17 +00:00
parent 9a11fba79f
commit ff18b9ff38
11 changed files with 75 additions and 18 deletions
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2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -8844,6 +8844,8 @@ static const struct {
{ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
{ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
{ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
{ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16,
ARM::FeatureNEON | ARM::FeatureCrypto},
{ARM::FP_ARMV8, ARM::FeatureFPARMv8,
ARM::FeatureNEON | ARM::FeatureCrypto},
{ARM::NEON, ARM::FeatureNEON, 0},