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Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert

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instruction at the end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-01-30 18:18:23 +00:00
parent 21b70b237d
commit ff9b373e8f
13 changed files with 23 additions and 39 deletions
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8
include/llvm/Target/TargetLowering.h
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@ -1022,13 +1022,13 @@ public:
// Scheduler hooks
//
// InsertAtEndOfBasicBlock - This method should be implemented by targets that
// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
// EmitInstrWithCustomInserter - This method should be implemented by targets
// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
// instructions are special in various ways, which require special support to
// insert. The specified MachineInstr is created but not inserted into any
// basic blocks, and the scheduler passes ownership of it to this method.
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
//===--------------------------------------------------------------------===//
// Addressing mode description hooks (used by LSR etc).

2
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -715,7 +715,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
} else {
// Insert this instruction into the end of the basic block, potentially
// taking some custom action.
BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
BB = DAG.getTargetLoweringInfo().EmitInstrWithCustomInserter(MI, BB);
}
// Additional results must be an physical register def.

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -3855,16 +3855,16 @@ void SelectionDAGLowering::visitFree(FreeInst &I) {
DAG.setRoot(Result.second);
}
// InsertAtEndOfBasicBlock - This method should be implemented by targets that
// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
// EmitInstrWithCustomInserter - This method should be implemented by targets
// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
// instructions are special in various ways, which require special support to
// insert. The specified MachineInstr is created but not inserted into any
// basic blocks, and the scheduler passes ownership of it to this method.
MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) {
cerr << "If a target marks an instruction with "
<< "'usesCustomDAGSchedInserter', it must implement "
<< "TargetLowering::InsertAtEndOfBasicBlock!\n";
<< "TargetLowering::EmitInstrWithCustomInserter!\n";
abort();
return 0;
}

2
lib/Target/ARM/ARMISelLowering.cpp
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@ -1453,7 +1453,7 @@ SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
//===----------------------------------------------------------------------===//
MachineBasicBlock *
ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {

2
lib/Target/ARM/ARMISelLowering.h
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@ -82,7 +82,7 @@ namespace llvm {
virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
/// isLegalAddressingMode - Return true if the addressing mode represented

11
lib/Target/CellSPU/SPUISelLowering.cpp
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@ -2534,17 +2534,6 @@ SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
return SDOperand();
}
//===----------------------------------------------------------------------===//
// Other Lowering Code
//===----------------------------------------------------------------------===//
MachineBasicBlock *
SPUTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB)
{
return BB;
}
//===----------------------------------------------------------------------===//
// Target Optimization Hooks
//===----------------------------------------------------------------------===//

3
lib/Target/CellSPU/SPUISelLowering.h
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@ -114,9 +114,6 @@ namespace llvm {
const SelectionDAG &DAG,
unsigned Depth = 0) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
std::pair<unsigned, const TargetRegisterClass*>

2
lib/Target/IA64/IA64ISelLowering.h
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@ -66,8 +66,6 @@ namespace llvm {
/// (currently, only "ret void")
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
// XXX virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
// XXX MachineBasicBlock *MBB);
};
}

4
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -3124,8 +3124,8 @@ SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
//===----------------------------------------------------------------------===//
MachineBasicBlock *
PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
MI->getOpcode() == PPC::SELECT_CC_I8 ||

4
lib/Target/PowerPC/PPCISelLowering.h
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@ -260,8 +260,8 @@ namespace llvm {
const SelectionDAG &DAG,
unsigned Depth = 0) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*>

8
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -121,8 +121,8 @@ namespace {
LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG);
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
virtual const char *getTargetNodeName(unsigned Opcode) const;
};
@ -895,8 +895,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
}
MachineBasicBlock *
SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned BROpcode;
unsigned CC;

4
lib/Target/X86/X86ISelLowering.cpp
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@ -5383,8 +5383,8 @@ bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
//===----------------------------------------------------------------------===//
MachineBasicBlock *
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");

4
lib/Target/X86/X86ISelLowering.h
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@ -356,8 +356,8 @@ namespace llvm {
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
/// getTargetNodeName - This method returns the name of a target specific
/// DAG node.