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Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1022,13 +1022,13 @@ public:
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// Scheduler hooks
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//
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// InsertAtEndOfBasicBlock - This method should be implemented by targets that
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// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// EmitInstrWithCustomInserter - This method should be implemented by targets
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// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// instructions are special in various ways, which require special support to
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// insert. The specified MachineInstr is created but not inserted into any
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// basic blocks, and the scheduler passes ownership of it to this method.
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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//===--------------------------------------------------------------------===//
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// Addressing mode description hooks (used by LSR etc).
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@ -715,7 +715,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
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} else {
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// Insert this instruction into the end of the basic block, potentially
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// taking some custom action.
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BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
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BB = DAG.getTargetLoweringInfo().EmitInstrWithCustomInserter(MI, BB);
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}
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// Additional results must be an physical register def.
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@ -3855,16 +3855,16 @@ void SelectionDAGLowering::visitFree(FreeInst &I) {
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DAG.setRoot(Result.second);
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}
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// InsertAtEndOfBasicBlock - This method should be implemented by targets that
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// mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// EmitInstrWithCustomInserter - This method should be implemented by targets
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// that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
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// instructions are special in various ways, which require special support to
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// insert. The specified MachineInstr is created but not inserted into any
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// basic blocks, and the scheduler passes ownership of it to this method.
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MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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cerr << "If a target marks an instruction with "
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<< "'usesCustomDAGSchedInserter', it must implement "
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<< "TargetLowering::InsertAtEndOfBasicBlock!\n";
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<< "TargetLowering::EmitInstrWithCustomInserter!\n";
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abort();
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return 0;
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}
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@ -1453,7 +1453,7 @@ SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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switch (MI->getOpcode()) {
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@ -82,7 +82,7 @@ namespace llvm {
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// isLegalAddressingMode - Return true if the addressing mode represented
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@ -2534,17 +2534,6 @@ SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
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return SDOperand();
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}
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//===----------------------------------------------------------------------===//
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// Other Lowering Code
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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SPUTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB)
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{
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return BB;
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}
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//===----------------------------------------------------------------------===//
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// Target Optimization Hooks
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//===----------------------------------------------------------------------===//
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@ -114,9 +114,6 @@ namespace llvm {
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
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std::pair<unsigned, const TargetRegisterClass*>
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@ -66,8 +66,6 @@ namespace llvm {
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/// (currently, only "ret void")
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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// XXX virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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// XXX MachineBasicBlock *MBB);
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};
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}
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@ -3124,8 +3124,8 @@ SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
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MI->getOpcode() == PPC::SELECT_CC_I8 ||
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@ -260,8 +260,8 @@ namespace llvm {
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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@ -121,8 +121,8 @@ namespace {
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
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bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee,
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ArgListTy &Args, SelectionDAG &DAG);
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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};
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@ -895,8 +895,8 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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}
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MachineBasicBlock *
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SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) {
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const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
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unsigned BROpcode;
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unsigned CC;
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@ -5383,8 +5383,8 @@ bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *BB) {
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X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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@ -356,8 +356,8 @@ namespace llvm {
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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