6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-06 09:44:39 +00:00
Code Issues Projects Releases Wiki Activity

Fix both the test for zero and what we do if we have a zero for

Browse Source 
umulo legalization.

Fixes PR13839

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163856 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2012-09-13 23:24:02 +00:00
parent 331f64cd0d
commit ffaf69b8b1
2 changed files with 54 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -2265,12 +2265,15 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
// A divide for UMULO will be faster than a function call. Select to
// make sure we aren't using 0.
SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
RHS, DAG.getConstant(0, VT), ISD::SETNE);
RHS, DAG.getConstant(0, VT), ISD::SETEQ);
SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
DAG.getConstant(1, VT), RHS);
SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
ISD::SETNE);
Overflow = DAG.getNode(ISD::SELECT, dl, N->getValueType(1), isZero,
DAG.getConstant(0, N->getValueType(1)),
Overflow);
ReplaceValueWith(SDValue(N, 1), Overflow);
return;
}

50
test/CodeGen/X86/xmulo.ll Normal file
View File

@ -0,0 +1,50 @@
; RUN: llc %s -o - | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
target triple = "i386-apple-macosx10.8.0"
declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
declare i32 @printf(i8*, ...)
@.str = private unnamed_addr constant [10 x i8] c"%llx, %d\0A\00", align 1
define i32 @t1() nounwind {
; CHECK: t1:
; CHECK: movl $0, 12(%esp)
; CHECK: movl $0, 8(%esp)
; CHECK: movl $72, 4(%esp)
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 8)
%2 = extractvalue {i64, i1} %1, 0
%3 = extractvalue {i64, i1} %1, 1
%4 = zext i1 %3 to i32
%5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
ret i32 0
}
define i32 @t2() nounwind {
; CHECK: t2:
; CHECK: movl $0, 12(%esp)
; CHECK: movl $0, 8(%esp)
; CHECK: movl $0, 4(%esp)
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 0)
%2 = extractvalue {i64, i1} %1, 0
%3 = extractvalue {i64, i1} %1, 1
%4 = zext i1 %3 to i32
%5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
ret i32 0
}
define i32 @t3() nounwind {
; CHECK: t3:
; CHECK: movl $1, 12(%esp)
; CHECK: movl $-1, 8(%esp)
; CHECK: movl $-9, 4(%esp)
%1 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 9, i64 -1)
%2 = extractvalue {i64, i1} %1, 0
%3 = extractvalue {i64, i1} %1, 1
%4 = zext i1 %3 to i32
%5 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i32 0, i32 0), i64 %2, i32 %4)
ret i32 0
}