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Rename CreateRegForValue to CreateReg, and change its argument

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from a Value to a Type, because it doesn't actually care about
the Value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-07-01 03:55:39 +00:00
parent a528bc0e8a
commit ffda6bac11
5 changed files with 11 additions and 11 deletions
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2
lib/CodeGen/SelectionDAG/FastISel.cpp
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@ -1211,7 +1211,7 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
// by bailing out early, we may leave behind some dead instructions,
// since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
// own moves. Second, this check is necessary becuase FastISel doesn't
// use CreateRegForValue to create registers, so it always creates
// use CreateReg to create registers, so it always creates
// exactly one register for each non-void instruction.
EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {

10
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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@ -176,23 +176,23 @@ unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
/// CreateRegForValue - Allocate the appropriate number of virtual registers of
/// CreateReg - Allocate the appropriate number of virtual registers of
/// the correctly promoted or expanded types. Assign these registers
/// consecutive vreg numbers and return the first assigned number.
///
/// In the case that the given value has struct or array type, this function
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, V->getType(), ValueVTs);
ComputeValueVTs(TLI, Ty, ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value];
EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = MakeReg(RegisterVT);
if (!FirstReg) FirstReg = R;

4
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
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@ -121,12 +121,12 @@ public:
return ValueMap.count(V);
}
unsigned CreateRegForValue(const Value *V);
unsigned CreateReg(const Type *Ty);
unsigned InitializeRegForValue(const Value *V) {
unsigned &R = ValueMap[V];
assert(R == 0 && "Already initialized this value register!");
return R = CreateRegForValue(V);
return R = CreateReg(V->getType());
}
};

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -6164,7 +6164,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
unsigned &RegOut = ConstantsOut[C];
if (RegOut == 0) {
RegOut = FuncInfo.CreateRegForValue(C);
RegOut = FuncInfo.CreateReg(C->getType());
CopyValueToVirtualRegister(C, RegOut);
}
Reg = RegOut;
@ -6177,7 +6177,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
assert(isa<AllocaInst>(PHIOp) &&
FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
"Didn't codegen value into a register!??");
Reg = FuncInfo.CreateRegForValue(PHIOp);
Reg = FuncInfo.CreateReg(PHIOp->getType());
CopyValueToVirtualRegister(PHIOp, Reg);
}
}

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -730,7 +730,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
unsigned &R = FuncInfo->ValueMap[BI];
if (!R)
R = FuncInfo->CreateRegForValue(BI);
R = FuncInfo->CreateReg(BI->getType());
}
bool HadTailCall = false;