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Rename CreateRegForValue to CreateReg, and change its argument
from a Value to a Type, because it doesn't actually care about the Value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107383 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1211,7 +1211,7 @@ bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
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// by bailing out early, we may leave behind some dead instructions,
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// since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
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// own moves. Second, this check is necessary becuase FastISel doesn't
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// use CreateRegForValue to create registers, so it always creates
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// use CreateReg to create registers, so it always creates
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// exactly one register for each non-void instruction.
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EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
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if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
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@ -176,23 +176,23 @@ unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
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return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
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}
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/// CreateRegForValue - Allocate the appropriate number of virtual registers of
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/// CreateReg - Allocate the appropriate number of virtual registers of
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/// the correctly promoted or expanded types. Assign these registers
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/// consecutive vreg numbers and return the first assigned number.
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///
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/// In the case that the given value has struct or array type, this function
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/// will assign registers for each member or element.
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///
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unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, V->getType(), ValueVTs);
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ComputeValueVTs(TLI, Ty, ValueVTs);
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unsigned FirstReg = 0;
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
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EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
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unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
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unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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unsigned R = MakeReg(RegisterVT);
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if (!FirstReg) FirstReg = R;
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@ -121,12 +121,12 @@ public:
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return ValueMap.count(V);
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}
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unsigned CreateRegForValue(const Value *V);
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unsigned CreateReg(const Type *Ty);
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unsigned InitializeRegForValue(const Value *V) {
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unsigned &R = ValueMap[V];
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assert(R == 0 && "Already initialized this value register!");
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return R = CreateRegForValue(V);
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return R = CreateReg(V->getType());
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}
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};
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@ -6164,7 +6164,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
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if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
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unsigned &RegOut = ConstantsOut[C];
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if (RegOut == 0) {
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RegOut = FuncInfo.CreateRegForValue(C);
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RegOut = FuncInfo.CreateReg(C->getType());
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CopyValueToVirtualRegister(C, RegOut);
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}
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Reg = RegOut;
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@ -6177,7 +6177,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
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assert(isa<AllocaInst>(PHIOp) &&
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FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
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"Didn't codegen value into a register!??");
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Reg = FuncInfo.CreateRegForValue(PHIOp);
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Reg = FuncInfo.CreateReg(PHIOp->getType());
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CopyValueToVirtualRegister(PHIOp, Reg);
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}
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}
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@ -730,7 +730,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
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if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
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unsigned &R = FuncInfo->ValueMap[BI];
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if (!R)
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R = FuncInfo->CreateRegForValue(BI);
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R = FuncInfo->CreateReg(BI->getType());
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}
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bool HadTailCall = false;
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