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Switch more instructions over to using the asmprinter. Fix bugs in the emission
of in/out instructions (missing %'s on registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15393 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -260,39 +260,48 @@ def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
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// Input/Output Instructions...
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//
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def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX
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II<(ops), "in AL, DX">;
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def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
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II<(ops), "in AX, DX">;
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II<(ops), "in %AL, %DX">;
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def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
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II<(ops), "in %AX, %DX">;
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def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX
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II<(ops), "in EAX, DX">;
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II<(ops), "in %EAX, %DX">;
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let printImplicitDefsBefore = 1 in {
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def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>; // AL = in [I/O address]
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def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize; // AX = in [I/O address]
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def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>; // EAX = in [I/O address]
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}
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def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address]
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II<(ops i16imm:$port), "in %AL, $port">;
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def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address]
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II<(ops i16imm:$port), "in %AX, $port">;
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def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address]
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II<(ops i16imm:$port), "in %EAX, $port">;
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let printImplicitUsesAfter = 1 in {
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def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>,
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II<(ops), "out DX, AL">;
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def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
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II<(ops), "out DX, AX">;
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def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>,
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II<(ops), "out DX, EAX">;
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def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>;
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def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize;
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def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>;
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}
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def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>,
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II<(ops), "out %DX, %AL">;
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def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
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II<(ops), "out %DX, %AX">;
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def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>,
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II<(ops), "out %DX, %EAX">;
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def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>,
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II<(ops i16imm:$port), "out $port, %AL">;
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def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize,
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II<(ops i16imm:$port), "out $port, %AX">;
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def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>,
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II<(ops i16imm:$port), "out $port, %EAX">;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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//
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def MOV8rr : I <"mov", 0x88, MRMDestReg>;
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def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize;
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def MOV32rr : I <"mov", 0x89, MRMDestReg>;
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def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >;
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def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize;
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def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >;
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def MOV8rr : I <"mov", 0x88, MRMDestReg>,
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II<(ops R8:$dst, R8:$src), "mov $dst, $src">;
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def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize,
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II<(ops R16:$dst, R16:$src), "mov $dst, $src">;
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def MOV32rr : I <"mov", 0x89, MRMDestReg>,
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II<(ops R32:$dst, R32:$src), "mov $dst, $src">;
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def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >,
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II<(ops R8:$dst, i8imm:$src), "mov $dst, $src">;
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def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize,
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II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">;
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def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >,
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II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">;
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def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
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def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
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def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
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@ -439,8 +448,10 @@ def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
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// Logical operators...
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def AND8rr : I <"and", 0x20, MRMDestReg>,
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II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">;
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def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize;
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def AND32rr : I <"and", 0x21, MRMDestReg>;
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def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize,
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II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
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def AND32rr : I <"and", 0x21, MRMDestReg>,
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II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
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def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
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def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
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def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
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@ -509,11 +520,11 @@ def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
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// Shift instructions
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// FIXME: provide shorter instructions when imm8 == 1
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def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL, // R8 <<= cl
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II<(ops R8:$dst, R8:$src), "shl $dst, CL">;
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II<(ops R8:$dst, R8:$src), "shl $dst, %CL">;
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def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL, // R16 <<= cl
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II<(ops R16:$dst, R16:$src), "shl $dst, CL">;
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II<(ops R16:$dst, R16:$src), "shl $dst, %CL">;
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def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL, // R32 <<= cl
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II<(ops R32:$dst, R32:$src), "shl $dst, CL">;
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II<(ops R32:$dst, R32:$src), "shl $dst, %CL">;
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def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl
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def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl
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def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl
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@ -526,11 +537,11 @@ def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= i
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def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
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def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL, // R8 >>= cl
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II<(ops R8:$dst, R8:$src), "shr $dst, CL">;
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II<(ops R8:$dst, R8:$src), "shr $dst, %CL">;
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def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL, // R16 >>= cl
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II<(ops R16:$dst, R16:$src), "shr $dst, CL">;
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II<(ops R16:$dst, R16:$src), "shr $dst, %CL">;
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def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL, // R32 >>= cl
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II<(ops R32:$dst, R32:$src), "shr $dst, CL">;
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II<(ops R32:$dst, R32:$src), "shr $dst, %CL">;
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def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl
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def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl
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def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl
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