3 Commits

Author	SHA1	Message	Date
Daniel Sanders	b6569388b9	[mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them ... Summary: To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are explicitly tested. Depends on D3695 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3696 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-12 13:04:32 +00:00
Daniel Sanders	31546cd352	[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them ... Summary: This required a new instruction group representing the 32-bit subset of MIPS-V that was available in MIPS32R2 Most of these instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. It happens because many of the MIPS V instructions have not been implemented. Depends on D3694 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546 91177308-0d34-0410-b5e6-96231b3b80d8	2014-05-12 12:52:44 +00:00
Daniel Sanders	769a6f2116	[mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's ... Summary: test/MC/Mips/<isa1>/invalid-<isa2>.s Test that <isa1> does not support <isa2>'s instructions. test/MC/Mips/<isa1>/invalid-<isa2>-xfail.s Things that should be invalid but currently aren't. Will XPASS if any become invalid. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538 91177308-0d34-0410-b5e6-96231b3b80d8	2014-04-03 14:14:22 +00:00