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3 Commits

Author SHA1 Message Date
JF Bastien
1ff585db47 WebAssembly: start instructions 
Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 23:41:25 +00:00
Dan Gohman
1efcdba0e2 [WebAssembly] Define separate Target instances for 32-bit and 64-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241193 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-01 21:42:34 +00:00
Dan Gohman
a74341308f [WebAssembly] Initial WebAssembly backend 
This WebAssembly backend is just a skeleton at this time and is not yet
functional.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241022 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-29 23:51:55 +00:00