Misha Brukman
|
86fd274790
|
* Enable allocation of registers r2-r10
* Allocate registers 13-31 backwards (to be able to store them all at once)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14896 91177308-0d34-0410-b5e6-96231b3b80d8
|
2004-07-16 20:35:20 +00:00 |
|
Misha Brukman
|
15eb0a15e5
|
* Do not allocate r0 as we use it indiscriminantly in the instr selector.
* Do not define CR register class because we don't (yet) have the i4 type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14551 91177308-0d34-0410-b5e6-96231b3b80d8
|
2004-07-01 21:24:50 +00:00 |
|
Misha Brukman
|
da7515a378
|
* Allow more registers to be allocated from the general register pool
* Define the condition register class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14510 91177308-0d34-0410-b5e6-96231b3b80d8
|
2004-06-30 21:54:50 +00:00 |
|
Misha Brukman
|
8ee0100880
|
Only allocate non-volatile registers R13-31 (for now).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14500 91177308-0d34-0410-b5e6-96231b3b80d8
|
2004-06-29 23:35:32 +00:00 |
|
Misha Brukman
|
5dfe3a9c3b
|
Initial revision
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
|
2004-06-21 16:55:25 +00:00 |
|