Commit Graph

111793 Commits

Author SHA1 Message Date
Hal Finkel
139bfee84c [PowerPC] Enable late partial unrolling on the POWER7
The P7 benefits from not have really-small loops so that we either have
multiple dispatch groups in the loop and/or the ability to form more-full
dispatch groups during scheduling. Setting the partial unrolling threshold to
44 seems good, empirically, for the P7. Compared to using no late partial
unrolling, this yields the following test-suite speedups:

SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding
	-66.3253% +/- 24.1975%
SingleSource/Benchmarks/Misc-C++/oopack_v1p8
	-44.0169% +/- 29.4881%
SingleSource/Benchmarks/Misc/pi
	-27.8351% +/- 12.2712%
SingleSource/Benchmarks/Stanford/Bubblesort
	-30.9898% +/- 22.4647%

I've speculatively added a similar setting for the P8. Also, I've noticed that
the unroller does not quite calculate the unrolling factor correctly for really
tiny loops because it neglects to account for the fact that not every loop body
replicant contains an ending branch and counter increment. I'll fix that later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225522 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 15:51:16 +00:00
Toma Tabacu
bdab504afd [mips] Add comment which explains why we need to change the assembler options before and after inline asm blocks. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 15:00:30 +00:00
Suyog Sarda
df970d6297 Assumption that "VectorizedValue" will always be an Instruction is not correct.
It can be a constant or a vector argument.

ex :

define i32 @hadd(<4 x i32> %a) #0 {
entry:
  %vecext = extractelement <4 x i32> %a, i32 0
  %vecext1 = extractelement <4 x i32> %a, i32 1
  %add = add i32 %vecext, %vecext1
  %vecext2 = extractelement <4 x i32> %a, i32 2
  %add3 = add i32 %add, %vecext2
  %vecext4 = extractelement <4 x i32> %a, i32 3
  %add5 = add i32 %add3, %vecext4
  ret i32 %add5
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225517 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 10:23:48 +00:00
Saleem Abdulrasool
c2a1df7125 ARM: add support for R_ARM_ABS16
Add support for R_ARM_ABS16 relocation mapping.  Addresses PR22156.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225510 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 06:57:24 +00:00
Saleem Abdulrasool
466a7dea9b test: add additional test for SVN r225507
Add an additional test case to ensure that we generate the relocation even if
the thumb target is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 06:57:18 +00:00
Saleem Abdulrasool
ea4fe48b22 ARM: add support for R_ARM_ABS8 relocations
Add support for R_ARM_ABS8 relocation.  Addresses PR22126.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225507 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 05:59:12 +00:00
Matthias Braun
c41acffe22 RegisterCoalescer: Fix removeCopyByCommutingDef with subreg liveness
The code that eliminated additional coalescable copies in
removeCopyByCommutingDef() used MergeValueNumberInto() which internally
may merge A into B or B into A. In this case A and B had different Def
points, so we have to reset ValNo.Def to the intended one after merging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225503 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 03:01:31 +00:00
Matthias Braun
4493e98154 RegisterCoalescer: Some cleanup in removeCopyByCommutingDef(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225502 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 03:01:28 +00:00
Matthias Braun
fdddd47cc6 RegisterCoalescer: No need to set kill flags, they are recompute later anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225501 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 03:01:26 +00:00
Matthias Braun
c25a1509c3 RegisterCoalescer: Turn some impossible conditions into asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225500 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 03:01:23 +00:00
Duncan P. N. Exon Smith
acec33834b Bitcode: Share logic for last instruction, NFC
Share logic for getting the last instruction emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225499 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 02:51:45 +00:00
Duncan P. N. Exon Smith
97bbaa3227 Bitcode: Move the DEBUG_LOC record to DEBUG_LOC_OLD
Prepare to simplify the `DebugLoc` record.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225498 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 02:48:48 +00:00
Hal Finkel
cc7ea4df1e [PowerPC] Add a flag for experimenting with subreg liveness tracking
This cannot yet be enabled by default, it causes ~50 miscompiles in the test
suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225497 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 02:03:11 +00:00
Hal Finkel
4e98296890 [PowerPC] Fold [sz]ext with fp_to_int lowering where possible
On modern cores with lfiw[az]x, we can fold a sign or zero extension from i32
to i64 into the load necessary for an i64 -> fp conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225493 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 01:34:30 +00:00
Hal Finkel
8e1d151abe [DAGCombine] Remainder of fix to r225380 (More FMA folding opportunities)
As pointed out by Aditya (and Owen), when we elide an FP extend to form an FMA,
we need to extend the incoming operands so that the resulting node will really
be legal. This is currently enabled only for PowerPC, and it happens to work
there regardless, but this should fix the functionality for everyone else
should anyone else wish to use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225492 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 01:29:29 +00:00
Chandler Carruth
72dd2f22b5 [x86] Add a flag to control the vector shuffle legality predicates that
complements the new vector shuffle lowering code path. This flag,
naturally, is *off* because we've not tested or evaluated the results of
this at all. However, the flag will make it much easier to evaluate
whether we can be this aggressive and whether there are missing vector
shuffle lowering optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225491 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 01:24:36 +00:00
Chandler Carruth
f3c718e49b Cleaup ValueHandle to no longer keep a PointerIntPair for the Value*.
This was used previously for metadata but is no longer needed there. Not
doing this simplifies ValueHandle and will make it easier to fix things
like AssertingVH's DenseMapInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225487 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 00:48:47 +00:00
Hal Finkel
40ddb2ce8f Partial fix to r225380 (More FMA folding opportunities)
As pointed out by Aditya (and Owen), there are two things wrong with this code.
First, it adds patterns which elide FP extends when forming FMAs, and that might
not be profitable on all targets (it belongs behind the pre-existing
aggressive-FMA-formation flag). This is fixed by this change.

Second, the resulting nodes might have operands of different types (the
extensions need to be re-added). That will be fixed in the follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225485 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 00:45:54 +00:00
Philip Reames
ce0e12f0b4 [REFACTOR] Push logic from MemDepPrinter into getNonLocalPointerDependency
Previously, MemDepPrinter handled volatile and unordered accesses without involving MemoryDependencyAnalysis.  By making a slight tweak to the documented interface - which is respected by both callers - we can move this responsibility to MDA for the benefit of any future callers.  This is basically just cleanup.

In the future, we may decide to extend MDA's non local dependency analysis to return useful results for ordered or volatile loads.  I believe (but have not really checked in detail) that local dependency analyis does get useful results for ordered, but not volatile, loads.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225483 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 00:26:45 +00:00
Hans Wennborg
d4ca466ed6 ReleaseNotes.rst: these are for 3.6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225482 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 00:21:26 +00:00
Philip Reames
dba2d12578 [Refactor] Have getNonLocalPointerDependency take the query instruction
Previously, MemoryDependenceAnalysis::getNonLocalPointerDependency was taking a list of properties about the instruction being queried. Since I'm about to need one more property to be passed down through the infrastructure - I need to know a query instruction is non-volatile in an inner helper - fix the interface once and for all.

I also added some assertions and behaviour clarifications around volatile and ordered field accesses. At the moment, this is mostly to document expected behaviour. The only non-standard instructions which can currently reach this are atomic, but unordered, loads and stores. Neither ordered or volatile accesses can reach here.

The call in GVN is protected by an isSimple check when it first considers the load. The calls in MemDepPrinter are protected by isUnordered checks. Both utilities also check isVolatile for loads and stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225481 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-09 00:04:22 +00:00
Duncan P. N. Exon Smith
cce3a8acec LangRef: Add usage points for distinct MDNodes
Omission pointed out by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225479 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 23:50:26 +00:00
Duncan P. N. Exon Smith
f081ff786f IR: Drop TODO now that PR22111 is finished
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225477 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:43:19 +00:00
Duncan P. N. Exon Smith
3408708548 Utils: Keep distinct MDNodes distinct in MapMetadata()
Create new copies of distinct `MDNode`s instead of following the
uniquing `MDNode` logic.

Just like self-references (or other cycles), `MapMetadata()` creates a
new node.  In practice most calls use `RF_NoModuleLevelChanges`, in
which case nothing is duplicated anyway.

Part of PR22111.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225476 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:42:30 +00:00
Duncan P. N. Exon Smith
f416d72973 IR: Add 'distinct' MDNodes to bitcode and assembly
Propagate whether `MDNode`s are 'distinct' through the other types of IR
(assembly and bitcode).  This adds the `distinct` keyword to assembly.

Currently, no one actually calls `MDNode::getDistinct()`, so these nodes
only get created for:

  - self-references, which are never uniqued, and
  - nodes whose operands are replaced that hit a uniquing collision.

The concept of distinct nodes is still not quite first-class, since
distinct-ness doesn't yet survive across `MapMetadata()`.

Part of PR22111.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225474 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:38:29 +00:00
Sanjay Patel
1cbba214c7 remove function names from comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225473 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:36:56 +00:00
Hal Finkel
b7c01bf403 [PowerPC] Mark all instructions as non-cheap for MachineLICM
MachineLICM uses a callback named hasLowDefLatency to determine if an
instruction def operand has a 'low' latency. If all relevant operands have a
'low' latency, the instruction is considered too cheap to hoist out of loops
even in low-register-pressure situations. On PowerPC cores, both the embedded
cores and the others, there is no reason to believe that this is a good choice:
all instructions have a cost inside a loop, and hoisting them when not limited
by register pressure is a reasonable default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225471 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:11:49 +00:00
Hal Finkel
9d1500e68f [MachineLICM] A command-line option to hoist even cheap instructions
Add a command-line option to enable hoisting even cheap instructions (in
low-register-pressure situations). This is turned off by default, but has
proved useful for testing purposes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225470 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 22:10:48 +00:00
Duncan P. N. Exon Smith
089a4ba180 CodeGen: Use handy new-fangled post-increment, NFC
Drive-by cleanup; I noticed this when reviewing the patch that became
r225466.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225468 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 21:07:55 +00:00
Akira Hatanaka
40cd57eb5c [ARM] Fix a bug in constant island pass that was triggering an assertion.
The assert was being triggered when the distance between a constant pool entry
and its user exceeded the maximally allowed distance after thumb2 branch
shortening. A padding was inserted after a thumb2 branch instruction was shrunk,
which caused the user to be out of range. This is wrong as the padding should
have been inserted by the layout algorithm so that the distance between two
instructions doesn't grow later during thumb2 instruction optimization.

This commit fixes the code in ARMConstantIslands::createNewWater to call
computeBlockSize and set BasicBlock::Unalign when a branch instruction is
inserted to create new water after a basic block. A non-zero Unalign causes
the worst-case padding to be inserted when adjustBBOffsetsAfter is called to
recompute the basic block offsets.

rdar://problem/19130476


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225467 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 20:44:50 +00:00
Duncan P. N. Exon Smith
8826cb9526 CodeGen: Use range-based for loops, NFC
Patch by Ramkumar Ramachandra!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225466 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 20:44:33 +00:00
Matt Arsenault
3b1f741856 Fix fcmp + fabs instcombines when using the intrinsic
This was only handling the libcall. This is another example
of why only the intrinsic should ever be used when it exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225465 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 20:09:34 +00:00
Eric Christopher
aa73f89bba The Kaleidoscope tutorial should be using "mcjit" for the library,
"jit" doesn't exist anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 19:07:01 +00:00
Lang Hames
1b3d915de6 [MCJIT] Remove a few redundant MCJIT tests, and drop the extraneous datalayout
strings from the copies that remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225460 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 18:52:15 +00:00
Eric Christopher
2c470a92e2 Make the TargetMachine in MipsSubtarget a reference rather
than a pointer to make unifying code a bit easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225459 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 18:18:57 +00:00
Eric Christopher
8ea074b518 Update include - this class doesn't use the target machine, but
only the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225458 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 18:18:54 +00:00
Eric Christopher
4ee6e6993f Fix a couple of odd formatting issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225457 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 18:18:53 +00:00
Eric Christopher
78a726e36d This routine is in InstrInfo, there's no need to access it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225456 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 18:18:50 +00:00
Ahmed Bougacha
3df0ee1141 [X86] Reflow comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225455 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 17:49:48 +00:00
Rafael Espindola
e8d9f7b5d1 clang-format. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225454 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 16:25:01 +00:00
Rafael Espindola
8aab70ebfe Make this test a bit stricter.
It now checks for the end of the line or the opening '{'.
While at it, remove empty comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225451 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 16:11:18 +00:00
Justin Hibbits
77e85a150c Add saving and restoring of r30 to the prologue and epilogue, respectively
Summary: The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register).  This does that.

Test Plan: Tests updated.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225450 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:47:19 +00:00
Rafael Espindola
f5aa68179c Explicitly handle LinkOnceODRAutoHideLinkage. NFC. We already have a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225449 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:39:50 +00:00
Rafael Espindola
b67f18b2d8 Update naming style and clang-format. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225448 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:36:32 +00:00
Kristof Beyls
d1cee9b3bc Fix large stack alignment codegen for ARM and Thumb2 targets
This partially fixes PR13007 (ARM CodeGen fails with large stack
alignment): for ARM and Thumb2 targets, but not for Thumb1, as it
seems stack alignment for Thumb1 targets hasn't been supported at
all.

Producing an aligned stack pointer is done by zero-ing out the lower
bits of the stack pointer. The BIC instruction was used for this.
However, the immediate field of the BIC instruction only allows to
encode an immediate that can zero out up to a maximum of the 8 lower
bits. When a larger alignment is requested, a BIC instruction cannot
be used; llvm was silently producing incorrect code in this case.

This commit fixes code generation for large stack aligments by
using the BFC instruction instead, when the BFC instruction is
available.  When not, it uses 2 instructions: a right shift,
followed by a left shift to zero out the lower bits.

The lowering of ARM::Int_eh_sjlj_dispatchsetup still has code
that unconditionally uses BIC to realign the stack pointer, so it
very likely has the same problem. However, I wasn't able to
produce a test case for that. This commit adds an assert so that
the compiler will fail the assert instead of silently generating
wrong code if this is ever reached.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225446 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:09:14 +00:00
Tom Stellard
9a6e4f08fe R600/SI: Remove SIISelLowering::legalizeOperands()
Its functionality has been replaced by calling
SIInstrInfo::legalizeOperands() from
SIISelLowering::AdjstInstrPostInstrSelection() and running the
SIFoldOperands and SIShrinkInstructions passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225445 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 15:08:17 +00:00
Elena Demikhovsky
6e8b53da17 Masked Load/Store - fixed a bug in type legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225441 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 12:29:19 +00:00
Michael Kuperstein
477eba5f81 Fix a think-o in the test for r225438.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225440 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 12:05:02 +00:00
Michael Kuperstein
757d230f7d Fix include ordering, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225439 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 11:59:43 +00:00
Michael Kuperstein
0858c28ca8 [X86] Don't try to generate direct calls to TLS globals
The call lowering assumes that if the callee is a global, we want to emit a direct call.
This is correct for regular globals, but not for TLS ones.

Differential Revision: http://reviews.llvm.org/D6862

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225438 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 11:50:58 +00:00