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Author SHA1 Message Date
Chad Rosier
33e528d44d [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 17:08:51 +00:00
Silviu Baranga
5c062ad926 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 15:54:56 +00:00
Silviu Baranga
8da7a4668f test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 13:12:38 +00:00
Richard Barton
db9ca59759 Test Commit - add a newline 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153083 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 10:50:35 +00:00
Bill Wendling
21e42d0ea5 It's possible to have a constant expression who's size is quite big (e.g., 
i128). In that case, we may not be able to print out the MCExpr as an
expression. For instance, we could have an MCExpr like this:

    0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64)

The MCExpr printer handles sizes up to 64-bits, but this expression would
require 128-bits. In this situation, try to evaluate the constant expression and
emit that as the value into 64-bit chunks.
<rdar://problem/11070338>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 08:56:43 +00:00
Craig Topper
89f4e6639d Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 07:17:59 +00:00
Craig Topper
a1ffc681ed Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153079 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 06:42:26 +00:00
Craig Topper
0c9da210f7 When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 05:28:39 +00:00
Eric Christopher
8c5293c955 Do everything up to generating code to try to get a register for 
a variable. The previous code would break the debug info changing
code invariant. This will regress debug info for arguments where
we elide the alloca created.

Fixes rdar://11066468

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153074 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 01:07:58 +00:00
Eric Christopher
c415af225d Untabify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153073 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 01:07:56 +00:00
Eric Christopher
4476bae1b4 Add another debugging statement here. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153072 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 01:07:53 +00:00
Eric Christopher
4e27027562 Use lookUpRegForValue here instead of duplicating the code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153071 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-20 01:07:47 +00:00
Chris Lattner
1aa73cc05a Fix two bugpoint bugs: 
1) opt is not usually in the same path as the target program. Even for
the bugpoint as a standalone app, it should be more portable to search
in PATH, isn't it?
2) bugpoint driver accounts opt plugins, but does not list them in the
final output command.

Patch by Dmitry Mikushin!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153066 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 23:42:11 +00:00
Chris Lattner
e0ac6f8a7d fix PR12301 - llvm-bcanalyze should print to stdout, not stderr (except for errors). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153065 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 23:40:48 +00:00
Pete Cooper
cfe2998c3e f16 FDIV can now be legalized by promoting to f32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 23:38:12 +00:00
Chris Lattner
e59b0e777d fix a build failure with libc++ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 23:31:01 +00:00
Jim Grosbach
fa1f74470a ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153055 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 21:32:32 +00:00
Jim Grosbach
ceee984302 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153053 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 20:39:53 +00:00
Michael J. Spencer
1f6e3f9544 [Object/COFF]: Expose getSectionContents. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153051 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 20:27:37 +00:00
Michael J. Spencer
b35a896e07 [Object/COFF]: Expose getSectionName. 
Also add some documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153050 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 20:27:15 +00:00
Anton Korobeynikov
2d7ea04e28 Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 19:19:50 +00:00
Lang Hames
23f1cbbd68 Add an option to the MI scheduler to cut off scheduling after a fixed number of 
instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153045 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 18:38:38 +00:00
Kostya Serebryany
8c0134a776 [asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- they are currently used only for experiments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153040 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 16:40:35 +00:00
NAKAMURA Takumi
5587a8e094 llvm/test/DebugInfo: Move two tests to DebugInfo/X86. They are X86-dependent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153038 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 16:16:03 +00:00
Duncan Sands
00294caadb Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 15:35:44 +00:00
Preston Gurd
3e99b715d1 This patch adds X86 instruction itineraries for non-pseudo opcodes in 
X86InstrCompiler.td.
 
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 14:10:12 +00:00
Benjamin Kramer
8118c94a55 Add a note for -ffast-math optimization of vector norm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153031 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-19 00:43:34 +00:00
Chandler Carruth
a87a75fd80 Make the formatting of this file more consistent, and fix the 80-columns 
violations I introduced. Also sort some of the instructions to get
a more consistent ordering.

Suggestions on still better / more consistent formatting would be
welcome. I'm actually tempted to use a macro to define all of the
delegate methods...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153030 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 23:45:14 +00:00
Chandler Carruth
080b862e67 Teach InstVisitor about the UnaryInstruction layer in the instruction 
type hierarchy. I wanted to use this for the inline cost rewrite, and
found it was missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153029 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 23:31:28 +00:00
Nick Lewycky
f201a06662 Factor out the multiply analysis code in ComputeMaskedBits and apply it to the 
overflow checking multiply intrinsic as well.

Add a test for this, updating the test from grep to FileCheck.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153028 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 23:28:48 +00:00
Craig Topper
97327dc6ef isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153027 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 22:50:10 +00:00
Nick Lewycky
75d05e6121 This clause (although matching parts of the implementation) can't be correct. 
Thanks to Eli for noticing the discrepancy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153011 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-18 09:35:50 +00:00
Benjamin Kramer
cff4ad768e CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 20:22:57 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 18:46:09 +00:00
Benjamin Kramer
85f9cef27e MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty. 
This is particularly helpful as both arguments tend to be constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152991 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 17:03:45 +00:00
Craig Topper
70de1e442d Fix some copy and paste remnants of Cell and SPU in Hexagon files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152981 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:39:20 +00:00
Craig Topper
8aea2dd964 Fix typo in file header. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152980 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:28:37 +00:00
Craig Topper
1e0c9ab0d1 Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152979 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 09:24:09 +00:00
Craig Topper
c1f6f42049 Reorder includes to match coding standards. Fix an issue or two exposed by that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 07:33:42 +00:00
Jim Grosbach
ae151ed87d MC asm parser macro argument count was wrong when empty. 
evaluated to '1' when the argument list was empty (should be '0').

rdar://11057257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152967 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 00:11:42 +00:00
Bill Wendling
5aeff3171c Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152959 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 23:11:07 +00:00
Francois Pichet
391c14530b Revert r152915. Chapuni's WinWaitReleased refactoring: It doesn't work for me 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152958 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 22:50:01 +00:00
Chris Lattner
748c1ec713 clarify the coding standards a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152957 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 22:34:37 +00:00
Jim Grosbach
11d5dc3d50 ARM fix silly typo in optional operand alias. 
rdar://11065671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 22:18:29 +00:00
Jim Grosbach
66cba302f0 ARM divided syntax fmrx/fmxr mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 21:06:13 +00:00
Jim Grosbach
be7cf2b377 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 20:48:38 +00:00
Bill Wendling
0ccae0b1f6 Revert r152907. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 18:20:54 +00:00
Benjamin Kramer
a82d526b31 ScheduleDAGInstrs: When adding uses we add them into a set that's empty at the beginning, no need to maintain another set for the added regs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152934 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 17:38:19 +00:00
Benjamin Kramer
861ea230a7 Limit the number of memory operands in MachineInstr to 2^16 and store the number in padding. 
Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152930 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 16:39:27 +00:00
Benjamin Kramer
87f3dbc446 CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the cached value. 
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-16 15:46:47 +00:00