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5 Commits

Author SHA1 Message Date
Dan Gohman
8c2d270ae8 Change the default scheduler from Latency to ILP, since Latency 
is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:45:02 +00:00
Akira Hatanaka
33ff5aeaa8 Fix test cases. 
Generate code for Mips32r1 unless a Mips32r2 feature is tested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 23:14:58 +00:00
Bill Wendling
d5941195e2 Better fix for this testcase. Update it to the new EH scheme entirely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 21:27:08 +00:00
Bill Wendling
cc6927b9e1 Update for new EH stuff. (I'm not sure if this is 100% correct.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 21:24:17 +00:00
Akira Hatanaka
8464fff30b Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue: 
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 02:17:21 +00:00