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80 Commits

Author SHA1 Message Date
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 19:45:41 +00:00
Matt Arsenault
e3e086ea00 Use .data() instead of &x[0] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205722 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 16:44:24 +00:00
Matt Arsenault
193c3e91b9 R600: Compute masked bits for min and max 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205242 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 19:35:33 +00:00
Matt Arsenault
828bfc7350 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205236 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 18:21:18 +00:00
Matt Arsenault
894fa802f5 R600: Add target nodes for BFM and BFI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 18:21:13 +00:00
Matt Arsenault
0c6d96cf16 R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:31 +00:00
Matt Arsenault
94687c0f43 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204945 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:24 +00:00
Matt Arsenault
e0e503801f R600: Add a testcase for sext_in_reg I missed. 
This sext_inreg i32 in i64 case was already handled, but not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-26 18:31:06 +00:00
Matt Arsenault
ab5382f5eb R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204743 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-25 18:18:27 +00:00
Matt Arsenault
6c199d8212 R600: Implement isNarrowingProfitable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 19:43:31 +00:00
Matt Arsenault
2683baa8ac R600: Match sign_extend_inreg to BFE instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 18:58:11 +00:00
Matt Arsenault
2345166d2f R600: Remove unnecessary attempt to zext a pointer. 
Private pointers are now always 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-15 00:08:26 +00:00
Matt Arsenault
2cf43de915 R600: Code cleanup. 
Use sign_extend_inreg and getZeroExtendInReg instead of
using the bit operations they expand into.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203988 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-15 00:08:22 +00:00
Matt Arsenault
054f4eccd2 R600: Fix trunc store from i64 to i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-12 18:45:52 +00:00
Matt Arsenault
0e5b4860b5 R600: Calculate store mask instead of using switch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203527 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-11 01:38:53 +00:00
Matt Arsenault
cc1240ee1b Use .data() instead of &x[0] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203516 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-11 00:01:31 +00:00
Matt Arsenault
161e3a80b2 R600: Fix extloads from i8 / i16 to i64. 
This appears to only be working for global loads. Private
and local break for other reasons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:12 +00:00
Matt Arsenault
b4cd160bb9 R600/SI: Expand selects on vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:03 +00:00
Matt Arsenault
af0cc459bf Fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203013 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-05 21:47:22 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 21:01:28 +00:00
Matt Arsenault
e87a1a9e2c Fix DOT4 missing from getTargetOpcodeName 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 21:01:21 +00:00
Tom Stellard
0f2e653317 R600/SI: Expand all v8[if]32 operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:15 +00:00
Benjamin Kramer
eee40f92a9 R600: Always implement both versions of isTruncateFree and add a sanity check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201222 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-12 10:17:54 +00:00
Matt Arsenault
700bba297b R600: Implement isTruncateFree 
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201107 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 19:57:42 +00:00
Tom Stellard
7d9ed1cac5 R600/SI: Expand i1 BR_CC 
This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.

I was unable to come up with a reduced test case for this.

https://bugs.freedesktop.org/show_bug.cgi?id=72785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200776 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-04 17:18:43 +00:00
Tom Stellard
4ee42eaec9 R600: Enable vector fpow. 
The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."

Patch by: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200773 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-04 17:18:37 +00:00
Tom Stellard
9c3e0ede1d R600: Add support for global addresses with constant initializers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199825 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 19:24:21 +00:00
Tom Stellard
7dd37ae57a R600/SI: Add support for i8 and i16 private loads/stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199823 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 19:24:14 +00:00
Tom Stellard
37ee312f77 R600: Allow ftrunc 
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-20 05:11:55 +00:00
Matt Arsenault
729e476834 Don't manually calculate size in bytes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197327 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-14 18:21:59 +00:00
Matt Arsenault
17427fa9bb Use llvm_unreachable instead of assert(0) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-10 21:37:42 +00:00
Tom Stellard
8a6b7df6f8 R600: Expand vector FABS 
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 21:23:39 +00:00
Tom Stellard
496dbfe7b9 R600: Add support for ISD::FROUND 
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 21:23:20 +00:00
Matt Arsenault
509a492442 Add target hook to prevent folding some bitcasted loads. 
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-15 04:42:23 +00:00
Tom Stellard
a2b4eb6d15 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 23:36:50 +00:00
Vincent Lejeune
69239a98b6 R600: Fix LowerUDIVREM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 17:36:04 +00:00
Tom Stellard
aa1d078e7f R600: Custom lower f32 = uint_to_fp i64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 17:22:05 +00:00
Tom Stellard
f54a8409f9 R600: Expand vector FSQRT ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193620 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-29 16:37:20 +00:00
Tom Stellard
f95b162188 R600: Fix handling of vector kernel arguments 
The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted.  In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-23 00:44:32 +00:00
Tom Stellard
a3c2bcf0ee R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback 
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.

The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.

The maximum number of input SGPRs is bumped to 17.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190575 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-12 02:55:14 +00:00
Tom Stellard
470c451574 R600: Fix incorrect LDS size calculation 
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-05 18:37:57 +00:00
Tom Stellard
d08a930361 R600: Add support for vector local memory loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:06:04 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:49 +00:00
Tom Stellard
7a0282daeb R600: Add support for v4i32 and v2i32 local stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189222 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:44 +00:00
Tom Stellard
da25cd3e6d SelectionDAG: Use correct pointer size when lowering function arguments v2 
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes.  The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.

This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.

v2:
  - Add more helper functions to TargetLoweringBase
  - Use CHECK-LABEL for tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:36 +00:00
Tom Stellard
5464a92861 R600: Remove unnecessary casts 
Spotted by Bill Wendling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188942 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-21 22:14:17 +00:00
Tom Stellard
3cae823f69 R600: Expand vector FRINT ops 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188598 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 23:51:33 +00:00
Tom Stellard
84c0bd9803 R600: Expand vector FFLOOR ops 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188597 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 23:51:29 +00:00
Tom Stellard
0991c314d7 R600: Expand vector float operations for both SI and R600 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 23:51:24 +00:00
Tom Stellard
30d84d8dfa R600: Add support for global vector loads with element types less than 32-bits 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188521 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:12:16 +00:00