Commit Graph

56 Commits

Author SHA1 Message Date
Tim Northover
7428539a1c AArch64: enable MCJIT and tests now that everything passes.
This removes dire warnings about AArch64 being unsupported and enables
the tests when appropriate on this platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:22 +00:00
Tim Northover
85829bb98a AArch64: implement first relocation required for MCJIT
R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so
is required to compile any function without the "nounwind" attribute.

This change implements very basic infrastructure in the RuntimeDyldELF
file and allows (for example) the test-shift.ll MCJIT test to pass
on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:59 +00:00
Tim Northover
bd121f5b3a Build system changes to enable MCJIT on AArch64
These changes just allow AArch64 to take part in the MCJIT world when
built correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:52 +00:00
Tim Northover
effc16bb49 AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:11 +00:00
Tim Northover
79c1c092df AArch64: support literal pool access in large memory model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:07 +00:00
Tim Northover
cd1b09b25b AArch64: support large code model for jump-tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:00 +00:00
Tim Northover
b2efdde06c AArch64: implement support for blockaddress in large code model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:53:53 +00:00
Tim Northover
45db92038b AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.

For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:53:46 +00:00
Jia Liu
297a3ee16e AArch64 InstrFormats:
delete blank.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-28 01:45:11 +00:00
Tim Northover
3e56b43ac8 AArch64: remove unnecessary check that RS is valid
AArch64 always demands a register-scavenger, so the pointer should never be
NULL. However, in the spirit of paranoia, we'll assert it before use just in
case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 06:55:15 +00:00
Tim Northover
75f013822b AArch64: remove useless comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179952 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 15:57:41 +00:00
Tim Northover
8b71994fde Remove unused ShouldFoldAtomicFences flag.
I think it's almost impossible to fold atomic fences profitably under
LLVM/C++11 semantics. As a result, this is now unused and just
cluttering up the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-20 12:32:43 +00:00
Peter Collingbourne
df39be6cb4 Add support for subsections to the ELF assembler. Fixes PR8717.
Differential Revision: http://llvm-reviews.chandlerc.com/D598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17 21:18:16 +00:00
David Majnemer
bae6d527df Fix undefined behavior in AArch64
A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to
execute shifts that perform undefined behavior. Instead of attempting
to perform the 64-bit rotation, treat it as a no-op.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11 20:13:52 +00:00
Tim Northover
211ffd242d AArch64: remove barriers from AArch64 atomic operations.
I've managed to convince myself that AArch64's acquire/release
instructions are sufficient to guarantee C++11's required semantics,
even in the sequentially-consistent case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 08:40:41 +00:00
Tim Northover
4385f5dfce AArch64: implement ETMv4 trace system registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 12:31:29 +00:00
Tim Northover
e94349fecf AArch64: switch patterns to be type-based rather than RegClass-based
It's a bit of churn in the blame log, but I think there are real benefits to
the newer system so I'm making the change in one go.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178633 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03 11:19:16 +00:00
Tim Northover
42a1b2f0b1 AArch64: implement GICv3 system registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 14:30:46 +00:00
Tim Northover
fe37e6279e Switch to LLVM support function abs64 to keep VS2008 happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 13:15:08 +00:00
Hal Finkel
dc3beb9017 Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-22 23:32:27 +00:00
Eric Christopher
a286fc065a Silence anonymous type in anonymous union warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 00:42:55 +00:00
Hal Finkel
0cc52c67db Move estimateStackSize from ARM into MachineFrameInfo
This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:15:20 +00:00
Tim Northover
69fe178f77 AArch64: expand sincos operations, we don't support them.
Patch based on Mans Rullgard's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 13:55:07 +00:00
Tim Northover
54a1cf75d2 AArch64: remove post-encoder method from FCMP (immediate) instructions.
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 14:46:14 +00:00
Tim Northover
6ff20f205b AArch64: be more careful resorting to inefficient addressing for weak vars.
If an otherwise weak var is actually defined in this unit, it can't be
undefined at runtime so we can use normal global variable sequences (ADRP/ADD)
to access it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176259 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 14:36:31 +00:00
Tim Northover
5366ab21f4 AArch64: don't drop GlobalAddress offset when handling extern_weak decls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 14:36:24 +00:00
Tim Northover
279b9184c2 AArch64: Use cbnz instead of cmp/b.ne pair for atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 13:52:07 +00:00
Francois Pichet
f4aa644dff Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175991 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-24 12:34:13 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 20:05:00 +00:00
Jim Grosbach
cb2ae3d98e MCParser: Update method names per coding guidelines.
s/AddDirectiveHandler/addDirectiveHandler/
s/ParseMSInlineAsm/parseMSInlineAsm/
s/ParseIdentifier/parseIdentifier/
s/ParseStringToEndOfStatement/parseStringToEndOfStatement/
s/ParseEscapedString/parseEscapedString/
s/EatToEndOfStatement/eatToEndOfStatement/
s/ParseExpression/parseExpression/
s/ParseParenExpression/parseParenExpression/
s/ParseAbsoluteExpression/parseAbsoluteExpression/
s/CheckForValidSection/checkForValidSection/

http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175675 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 22:21:35 +00:00
Chandler Carruth
2878b7d7ab Remove some unused private fields from the AArch64MCCodeEmitter. These
fields were only ever set in the constructor. The create method retains
its consistent interface so that these bits can be re-threaded through
the emitter if they're ever needed.

This was found by the -Wunused-private-field Clang warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 02:08:14 +00:00
David Blaikie
a39058aaed Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.
Also removes some redundant DNI comments on function declarations already
using the macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:11:17 +00:00
Benjamin Kramer
9831bf06e8 AArch64: Avoid shifts by 64, that's undefined behavior.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 17:55:32 +00:00
Tim Northover
85d2760c8e AArch64: add branch fixup pass.
This is essentially a stripped-down version of the ConstandIslands pass (which
always had these two functions), providing just the features necessary for
correctness.

In particular there needs to be a way to resolve the situation where a
conditional branch's destination block ends up out of range.

This issue crops up when self-hosting for AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 14:32:20 +00:00
Tim Northover
1e8839302b AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:43 +00:00
Tim Northover
148ac534fc AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 09:33:26 +00:00
Tim Northover
ad1b9dcb2c AArch64: switch from neverHasSideEffects to hasSideEffects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:31:12 +00:00
Tim Northover
5464c301c4 AArch64: stop claiming that NEON registers are usable for now.
If vector types have legal register classes, then LLVM bypasses LegalizeTypes
on them, which causes faults currently since the code to handle them isn't in
place.

This fixes test failures when AArch64 is the default target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:22:14 +00:00
Tim Northover
5bd6cb2dab AArch64: add block comments where missing
Only comments affected. No code change at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 16:17:01 +00:00
Tim Northover
716d26b2ce AArch64: fix build on some MSVC versions
This does two things:

It removes a call to abs() which may have "long long" parameter on Windows,
which is not necessarily available in C++03.

It also corrects the signedness of Amount, which was relying on
implementation-defined conversions previously.

Code was already tested (albeit in an implemnetation defined way) so no extra
tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 14:25:52 +00:00
Tim Northover
77b1c9cf57 AArch64: Simplify logic in deciding whether bfi is valid
Previous code had a confusing comment which was mostly an implementation
detail. This condition corresponds to "lsb up to register width" and "width not
ridiculous".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174877 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 12:32:18 +00:00
Tim Northover
b516186386 Make use of DiagnosticType to provide better AArch64 diagnostics.
This gives a DiagnosticType to all AsmOperands in sight. This replaces all
"invalid operand" diagnostics with something more specific. The messages given
should still be sufficiently vague that they're not usually actively misleading
when LLVM guesses your instruction incorrectly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-11 09:29:37 +00:00
Joel Jones
612779eb83 Spelling correction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174852 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-10 23:56:30 +00:00
Tim Northover
8a06229c89 Implement external weak (ELF) symbols on AArch64
Weakly defined symbols should evaluate to 0 if they're undefined at
link-time. This is impossible to do with the usual address generation
patterns, so we should use a literal pool entry to materlialise the
address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 16:43:33 +00:00
Tim Northover
cbff068398 Add AArch64 CRC32 instructions
These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 09:13:13 +00:00
Tim Northover
9e3b31345f Add icache prefetch operations to AArch64
This adds hints to the various "prfm" instructions so that they can
affect the instruction cache as well as the data cache.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-06 09:04:56 +00:00
Jakob Stoklund Olesen
baa3c50a7b Move MRI liveouts to AArch64 return instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 18:21:49 +00:00
Tim Northover
a693205ce1 Fix signed-unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 16:40:06 +00:00
Tim Northover
b9e1a33941 Fix remaining StringRef abuse.
This should fix the valgrind buildbot failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174375 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 15:01:51 +00:00
Tim Northover
dfe076af98 Fix formatting in AArch64 backend.
This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174370 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 13:24:56 +00:00