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18 Commits

Author SHA1 Message Date
Benjamin Kramer
1bfcd1f675 Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232998 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-23 19:32:43 +00:00
Eric Christopher
b56d7b0316 Cleanup and remove a chunk of getARMSubtarget calls in the 
ARM TargetMachine pass pipeline construction by pushing them down
into the appropriate pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231323 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-03-05 00:23:40 +00:00
Eric Christopher
9accb10855 Include map into the A15SDOptimizer rather than pick it up 
transitively from the DFAPacketizer via TargetInstrInfo.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219652 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 01:13:51 +00:00
Eric Christopher
6035518e3b Have MachineFunction cache a pointer to the subtarget to make lookups 
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-05 02:39:49 +00:00
Eric Christopher
9f85dccfc6 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-08-04 21:25:23 +00:00
Craig Topper
bd01df2487 Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211254 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-19 06:10:58 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-25 05:30:21 +00:00
Chandler Carruth
42e8630239 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE 
definition below all of the header #include lines, lib/Target/...
edition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206842 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-22 02:41:26 +00:00
Jim Grosbach
81fb6bfb85 Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205583 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 23:43:18 +00:00
Craig Topper
ac732eb207 Prune includes in ARM target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204548 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-22 23:51:00 +00:00
Hao Liu
19a3e9aabe [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204304 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 05:36:59 +00:00
Owen Anderson
bf63022492 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-13 23:12:04 +00:00
Craig Topper
d11898db4c [C++11] Add 'override' keyword to virtual methods that override their base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203433 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-10 02:09:33 +00:00
Chandler Carruth
974a445bd9 Re-sort all of the includes with ./utils/sort_includes.py so that 
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-07 11:48:04 +00:00
Alp Toker
087ab613f4 Correct word hyphenations 
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196471 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-05 05:44:44 +00:00
Jim Grosbach
1bfa80359e ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane. 
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:08:44 +00:00
Craig Topper
365ef0b197 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-03 15:07:05 +00:00
Silviu Baranga
bcbf3fddef Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-15 18:28:25 +00:00