- This avoids unnecessary malloc/free overhead in the common case, and
unnecessary copying from the ostream buffer into the output vector.
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- These allow clients to make use of the extra elements in the vector which
have already been allocated, without requiring them to be value initialized.
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gcc-4.4 was optimizing away comparisons against SimpleValueType when
it was compared to a value larger than the largest value in the enum.
This patch works around it by adding one extra item to the enum so
that these tests will now be valid.
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when trying to run opt in parallel. This lets parallel opt crunch 403.gcc in about a third
of the time.
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- Kill off begin(), end(), and iterator. It isn't clear what these
mean. Instead provide getBufferStart(), which can be used with
GetNumBytesInBuffer to the same effect.
- Update ComputeColumn to take arguments for the buffer to scan, this
simplifies the implementation of write_impl substantially.
- This should also fix possible problems with the scanning pointer pointing
outside of the current raw_ostream buffer.
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- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.
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TargetData is not present. It still uses TargetData when available.
This generalization also fixed some limitations in the TargetData
case; the attached testcase covers this.
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MCAsmStreamer. Based on this, eliminate the current section from AsmPrinter.
While I'm at it, clean up the last of the horrible "switch to null section" stuff
and add an assert. This change is in preparation for completely eliminating
asmprinter::switchtosection.
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more properly belong. This allows removing the front-end conditionalized
SJLJ code, and cleans up the generated IR considerably. All of the
infrastructure code (calling _Unwind_SjLj_Register/Unregister, etc) is
added by the SjLjEHPrepare pass.
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doing it directly. This requires const'izing a bunch of stuff that
took sections, but this seems like the right semantic thing to do:
emitting a label to a section shouldn't mutate the MCSection object
itself, for example.
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This also adds unit tests to APFloat that mainly tests the
string handling of APFloat, but not much else of it's api.
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
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libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
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In order for the changes in r78424 to work properly, cast_retty<X,Y> should return an object instead of a reference, and it's not clear that this approach has real advantages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79023 91177308-0d34-0410-b5e6-96231b3b80d8
specific printer (this only works on x86, for now).
- This makes it possible to do some correctness checking of the parsing and
matching, since we can compare the results of 'as' on the original input, to
those of 'as' on the output from llvm-mc.
- In theory, we could now have an easy ATT -> Intel syntax converter. :)
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TargetAsmInfo. This eliminates a dependency on TargetMachine.h from
TargetRegistry.h, which technically was a layering violation.
- Clients probably can only sensibly pass in the same TargetAsmInfo as the
TargetMachine has, but there are only limited clients of this API.
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unbuffered. std::ostream does its own buffering, and std::string and
SmallVector both have allocation strategies intended to handle frequent
appending.
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needs of the underlying output mechanism. raw_fd_ostream now uses
st_blksize from fstat to determine a buffer size.
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x86_64-apple-darwin10.
--- Reverse-merging r78895 into '.':
U test/CodeGen/PowerPC/2008-12-12-EH.ll
U lib/Target/DarwinTargetAsmInfo.cpp
--- Reverse-merging r78892 into '.':
U include/llvm/Target/DarwinTargetAsmInfo.h
U lib/Target/X86/X86TargetAsmInfo.cpp
U lib/Target/X86/X86TargetAsmInfo.h
U lib/Target/ARM/ARMTargetAsmInfo.h
U lib/Target/ARM/ARMTargetMachine.cpp
U lib/Target/ARM/ARMTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.cpp
U lib/Target/PowerPC/PPCTargetAsmInfo.h
U lib/Target/PowerPC/PPCTargetMachine.cpp
G lib/Target/DarwinTargetAsmInfo.cpp
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syntactically as a string, very similiar to what Chris did with MachO.
The parsing support and validation is not introduced yet.
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int x __attribute__((section("_foo, _bar"))) = 4;
int y __attribute__((section("_foo, _bar, 4byte_literals"))) = 1;
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There have been a few times where I've wanted this but ended up leaving the
operand type unconstrained. It is easy to add this now and should help
catch errors in the future.
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pair instead of from a virtual method on TargetMachine. This cuts the final
ties of TargetAsmInfo to TargetMachine, meaning that MC can now use
TargetAsmInfo.
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the darwin version string. This should help consolidate
the variety of weird functions we have scattered around the
codebase that do stuff like this.
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- Used to mark fake instructions which don't correspond to an actual machine
instruction (or are duplicates of a real instruction). This is to be used for
"special cases" in the .td files, which should be ignored by things like the
assembler and disassembler. We still need a good solution to handle pervasive
duplication, like with the Int_ instructions.
- Set the bit on fake "mov 0" style instructions, which allows turning an
assembler matcher warning into a hard error.
- -2 FIXMEs.
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version. This allows TAI implementations to specify the directive to use
based on the mode being codegen'd for.
The real fix for this is to remove JumpTableDirective, but I don't feel
like diving into the jumptable snarl just now.
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The register scavenger maintains a DistanceMap that maps MI pointers to their
distance from the top of the current MBB. The DistanceMap is built
incrementally in forward() and in bulk in findFirstUse(). It is used by
scavengeRegister() to determine which candidate register has the longest
unused interval.
Unfortunately the DistanceMap contents can become outdated. The first time
scavengeRegister() is called, the DistanceMap is filled to cover the MBB. If
then instructions are inserted in the MBB (as they always are following
scavengeRegister()), the recorded distances are too short. This causes bad
behaviour in the included test case where a register use /after/ the current
position is ignored because findFirstUse() thinks is is /before/ the current
position. A "using an undefined register" assertion follows promptly.
The fix is to build a fresh DistanceMap at the top of scavengeRegister(), and
discard it after use. This means that DistanceMap is no longer needed as a
RegScavenger member variable, and forward() doesn't need to update it.
The fix then discloses issue number two in the same test case: The candidate
search in scavengeRegister() finds a CSR that has been saved in the prologue,
but is currently unused. It would be both inefficient and wrong to spill such
a register in the emergency spill slot. In the present case, the emergency
slot restore is placed immediately before the normal epilogue restore, leading
to a "Redefining a live register" assertion.
Fix number two: When scavengerRegister() stumbles upon an unused register that
is overwritten later in the MBB, return that register early. It is important
to verify that the register is defined later in the MBB, otherwise it might be
an unspilled CSR.
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the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
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and short. Well, it's kinda short. Definitely nasty and brutish.
The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.
Built on Darwin and verified no llvm-core "make check" regressions.
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This definitely slows down asm output so put it under an -asm-exuberant
flag.
This information is useful when doing static analysis of performance
issues.
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instead of syntactically as a string. This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.
Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
S_GB_ZEROFILL segment type?
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take the table vectors as separate arguments, instead of the previous
approach where they were combined into one big vector.
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2. Move section switch printing to MCSection virtual method which takes a
TAI. This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
TLOFELF::AtIsCommentChar.
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A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.
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- Part of optimal static profiling patch sequence by Andreas Neustifter.
- Store edge, block, and function information separately for each functions
(instead of in one giant map).
- Return frequencies as double instead of int, and use a sentinel value for
missing information.
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Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations
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Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>
subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>
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Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
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as vector shuffles did not work out well. Shuffles that produce double-wide
vectors accurately represent the operation but make it hard to do anything
with the results. I considered splitting them up into 2 shuffles, one to
write each register separately, but there doesn't seem to be a good way to
reunite them for codegen.
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driven by TAI to being static, driven by tblgen. This means that a
target doesn't get impacted by this stuff at all if it doesn't opt
into it.
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The use case is if you have a wrapper class:
class Base {
void *Ptr;
public:
Base() : Ptr(0) { }
operator bool() const { return Ptr; }
.....
}
and sub-wrappers that have exactly the same size:
class Sub : public Base {
public:
....
static bool classof(const Base*);
}
and in the code you would do:
void f(Base b) {
Sub sub = dyn_cast<Sub>(b);
if (sub) {
....
}
}
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http://llvm.org/viewvc/llvm-project?view=rev&revision=78127, I'm changing the
ExecutionEngine's global mappings to hold AssertingVH<const GlobalValue>. That
way, if unregistering a mapping fails to actually unregister it, we'll get an
assert. Running the jit nightly tests didn't uncover any actual instances of
the problem.
This also uncovered the fact that AssertingVH<const X> didn't work, so I fixed
that too.
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LoopDependenceAnalysis::getLoops is currently O(N*M) for a loop-nest of
depth N and a compound SCEV of M atomic SCEVs. As both N and M will
typically be very small, this should not be a problem. If it turns out
to be one, rewriting getLoops as SCEVVisitor will reduce complexity to
O(M).
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creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.
1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
pure virtual method to assign sections to globals with a specified
section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
They are now all detangled and understandable, woo! :)
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- start support for new PEI w/reg alloc, allow running RS from emit{Pro,Epi}logue() target hooks.
- fix minor issue with recursion detection.
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just argv[0]. And remove the code for searching the current
working directory and for searching PATH; the point of FindExecutable
is not to find whatever version of the executable can be found by
searching around, but to find an executable that accompanies the
current executable.
Update the tools to use sys::Program::FindProgramByName when they
want PATH searching.
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