198 Commits

Author SHA1 Message Date
Matt Arsenault
a9da1cee40 R600/SI: Merge tables for commuting
Don't use a separate table for compares anymore,
and use the same VOP2_REV class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232992 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:41 +00:00
Matt Arsenault
7ec044c97b R600/SI: Move hasSideEffects setting into VOPCX classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232989 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:35 +00:00
Matt Arsenault
59a5e979b5 R600/SI: Allow commuting compares
This enables very common cases to switch to the
smaller encoding.

All of the standard LLVM canonicalizations of comparisons
are the opposite of what we want. Compares with constants
are moved to the RHS, but the first operand can be an inline
immediate, literal constant, or SGPR using the 32-bit VOPC
encoding.

There are additional bad canonicalizations that should
also be fixed, such as canonicalizing ge x, k to gt x, (k + 1)
if this makes k no longer an inline immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232988 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:30 +00:00
Matt Arsenault
3aaa5548e3 R600/SI: Remove cond operand to VOPCX classes
It isn't used, and these will probably never be directly selected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232986 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-23 18:45:20 +00:00
Tom Stellard
18e8ab1112 R600/SI: Refactor VOP2 instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-20 15:14:23 +00:00
Tom Stellard
fb9cd4bbd8 R600/SI: Refactor VOP1 instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-20 15:14:21 +00:00
Tom Stellard
d996c4b8ad R600/SI: Don't print scc reg in sopc assembly string
This is how the proprietary driver prints sopc instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232106 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 21:34:28 +00:00
Tom Stellard
3d712a6373 R600/SI: Remove _e32 and _e64 suffixes from mnemonics
Instead print them as part of the $dst operand.  The AsmMatcher
requires the 32-bit and 64-bit encodings have the same mnemonic in
order to parse them correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232105 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-12 21:34:22 +00:00
Tom Stellard
d472057ca2 R600/SI: Add _IDXEN and _BOTHEN variants for buffer_store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:51 +00:00
Tom Stellard
29e7485cda R600/SI: Re-order MUBUF operands to match asm strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:49 +00:00
Tom Stellard
92811fa2c7 R600/SI: Add 32-bit encoding of v_cndmask_b32
This was done by refactoring the v_cndmask_b32 tablegen definition
to use inherit from VOP2Inst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-10 16:16:44 +00:00
Tom Stellard
3db921673e R600/SI: Move gds operand to the end of operand list
Also print it in the assembly string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231684 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 18:49:54 +00:00
Tom Stellard
4c5aebe89d R600/SI: Refactor DS instruction defs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231683 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 18:49:45 +00:00
Tom Stellard
2ffe261575 R600/SI: Fix DS definitions and add missing instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231663 91177308-0d34-0410-b5e6-96231b3b80d8
2015-03-09 16:03:45 +00:00
Tom Stellard
27eab65932 R600/SI: Add missing mubuf instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 14:59:46 +00:00
Tom Stellard
a9c15883ba R600/SI: Consistently put soffset before the offset operand for mubuf instructions
This matches the assembly syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230758 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 14:59:44 +00:00
Tom Stellard
4ed3bf29cd R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230757 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 14:59:41 +00:00
Tom Stellard
89e4328381 R600/SI: Remove M0 from DS assembly strings
This matches the assembly syntax for the proprietary compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230645 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-26 17:08:43 +00:00
Matt Arsenault
dc9d5dcdd7 R600/SI: Fix mad*k definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230146 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-21 21:29:00 +00:00
Tom Stellard
d0da9ebb0a R600/SI: Don't set isCodeGenOnly = 1 on all instructions
We only need to set this on pseudo instructions which won't
be used by the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229689 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:08:17 +00:00
Tom Stellard
d1971ae8ba R600/SI: Add missing VOP1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229688 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:08:15 +00:00
Tom Stellard
585290a32a R600/SI: Add definition for S_CBRANCH_G_FORK
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:08:13 +00:00
Tom Stellard
fc0347ac9c R600/SI: Add missing SOP1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229685 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:08:11 +00:00
Tom Stellard
2ad48511fd R600/SI: Refactor SOP2 definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229684 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 16:08:09 +00:00
Matt Arsenault
4fd9c8677c R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change
them all to be consistently lowercase.

Now, non-encoding fields and convenience bits are capitalized.
Also remove weird looking empty line in some of the formats.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:35 +00:00
Matt Arsenault
abf19e5c1b R600/SI: Fix src1_modifiers for class instructions
src1 doesn't have modifiers, but the operand was missing
resulting in an encoding build error when all fields
are required.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:30 +00:00
Matt Arsenault
5177e9551c R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
Rename the multiclass since it now applies to the output
modifiers as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229610 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:15:27 +00:00
Matt Arsenault
76f78b9ac2 R600/SI: Fix encoding error from glc bit on VI SMRD instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:40 +00:00
Matt Arsenault
9e39c99180 R600/SI: Fix operand encoding for flat instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:37 +00:00
Matt Arsenault
642c65e2df R600/SI: Fix error from vdst on no return atomics
Set the ignored field to 0 so we can enable
noNamedPositionallyEncodedOperands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229606 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:10:35 +00:00
Matt Arsenault
2422768a8a R600/SI: Add missing offset operand to buffer bothen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229605 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:04:38 +00:00
Matt Arsenault
fe524d5902 R600/SI: Add missing soffset operand to global atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-18 02:04:35 +00:00
Matt Arsenault
9295d69bea R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.

Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229236 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-14 04:22:00 +00:00
Matt Arsenault
abcfb2b907 R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
This apparently got lost in the VI changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229230 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-14 03:40:35 +00:00
Matt Arsenault
124991cc67 R600/SI: Fix VOP3b encoding on VI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229228 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-14 03:02:23 +00:00
Tom Stellard
193679b6ae R600/SI: Refactor SOP1 classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229152 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-13 21:02:37 +00:00
Tom Stellard
1f85e3b090 R600/SI: Remove some unused TableGen classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229150 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-13 21:02:33 +00:00
Tom Stellard
6378a7cb0b R600/SI: Add soffset operand to mubuf addr64 instruction
We were previously hard-coding soffset to 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-11 00:34:32 +00:00
Michel Danzer
a7879dcf33 R600/SI: Also enable WQM for image opcodes which calculate LOD v3
If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.

v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228372 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-06 02:51:20 +00:00
Marek Olsak
f8cf57cb0c R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode
What this does is that if you accidentally select these instructions on VI,
the code generation will fail, because the pseudo -> _vi mapping will be
undefined.

The idea is to be able to catch possible future bugs easily.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 21:53:05 +00:00
Marek Olsak
e1a8ca95be R600/SI: Fix B64 VALU shifts on VI
SI only has standard versions. VI only has REV versions.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228037 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 21:53:01 +00:00
Marek Olsak
a95296a86e R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 17:38:12 +00:00
Marek Olsak
2ea95bd471 R600/SI: Remove VOP2_REV definitions from target-specific instructions
The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227989 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 17:38:05 +00:00
Marek Olsak
5e58a1bc29 R600/SI: Trivial instruction definition corrections for VI (v2)
- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.

- Define CVT_PK opcodes which are different between SI and VI. These are
  unused. The idea is to define all chip differences.

v2: keep V_MUL_LO_U32

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227988 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-03 17:38:01 +00:00
Eric Christopher
0def30471a Reuse a bunch of cached subtargets and remove getSubtarget calls
without a Function argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 23:24:40 +00:00
Marek Olsak
2ba0c13c26 R600/SI: Don't set patterns for chip-specific instructions while having pseudos
Only pseudos have patterns on them.

Also don't set the asm string for VINTRP_Pseudo. All pseudos should have empty
asm.

This matches what all other multiclasses do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227212 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:11 +00:00
Marek Olsak
9f824da16d R600/SI: Add VI versions of LDS atomics
Each class is split into two: one adds let statements around non-pseudos,
and the other one specifies the parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:07 +00:00
Marek Olsak
37788ca85a R600/SI: Add VI versions of MUBUF atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227210 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:25:02 +00:00
Marek Olsak
058ab6001b R600/SI: Add VI versions of MUBUF loads and stores
This enables a lot of existing patterns for VI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227209 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:24:58 +00:00
Marek Olsak
3111d0ae12 R600/SI: Add pseudos for MUBUF loads and stores
This defines the SI versions only, so it shouldn't change anything.

There are no changes other than using the new multiclasses, adding missing
mayLoad/mayStore, and formatting fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227208 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-27 17:24:54 +00:00