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10 Commits

Author SHA1 Message Date
Bob Wilson
f955f290c9 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:23:19 +00:00
Bob Wilson
20d8e4e7aa Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 23:24:25 +00:00
Bob Wilson
38aa2871fc Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-13 21:48:10 +00:00
Johnny Chen
52d2b0ed00 Thumb instructions which have reglist operands at the end and predicate operands 
before reglist were not properly handled with respect to IT Block.  Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly.  Add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-21 01:01:19 +00:00
Johnny Chen
56a1afb6b0 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12, 
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 18:45:24 +00:00
Johnny Chen
ef37e3abb7 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-20 17:28:50 +00:00
Johnny Chen
22e401f5d4 According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed.  That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.

Also add a test case for condition field '1111'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-19 21:19:52 +00:00
Benjamin Kramer
447b19543b unXFAIL, arm disassembler was reenabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-07 21:19:41 +00:00
Evan Cheng
1b0194d646 Reverting 100265 to try to get buildbots green again. Lots of self-hosting buildbots started complaining since this commit. Also xfail ARM disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-05 01:04:27 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen 
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-02 22:27:38 +00:00