* Add new RegisterOpt/RegisterAnalysis templates for registering passes that
are to show up in opt or analyze
* Register Analyses now
* Change optimizations to use RegisterOpt instead of RegisterPass
* Add support for different "PassType's"
* Add new RegisterOpt/RegisterAnalysis templates for registering passes that
are to show up in opt or analyze
* Register Analyses now
* Change optimizations to use RegisterOpt instead of RegisterPass
* Remove getPassName implementations from various subclasses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3112 91177308-0d34-0410-b5e6-96231b3b80d8
* Do NOT add a prefix to global variables that are external
* Add newline after emitting a constpointerref
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2925 91177308-0d34-0410-b5e6-96231b3b80d8
and generate actual machine instruction sequences directly.
Also a couple of bug fixes in code for putting constants into registers:
-- Do *not* sign-extend unsigned constant that is shorter than int reg size
-- Fix handling of address constant (a GlobalValue) vs. constant that
must be loaded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2856 91177308-0d34-0410-b5e6-96231b3b80d8
-- FP argument to a function with no prototype going on stack
was not being copied to the stack in colorCallArgs().
-- Put caller-saving code *before* argument copying code so that
we don't trash a register before saving it!
-- Two other minor fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2855 91177308-0d34-0410-b5e6-96231b3b80d8
changes in class MachineRegInfo (see MachineRegInfo.h for details).
Added {LD,ST}[X]FSR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2839 91177308-0d34-0410-b5e6-96231b3b80d8
basic block.
Mark setCCInstr used as dest. of conditional-move as both a def and a use.
BA instruction no longer has the unused CC argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2836 91177308-0d34-0410-b5e6-96231b3b80d8
handle conditional move instructions:
-- cpMem<->Reg functions now support CC registers (int and FP) correctly.
Also, cpMem<->Reg functions now return a vector of machine instructions.
-- Scratch registers must be explicitly provided to cpMem<->Reg when
needed, since CC regs need one to be copied to/from memory.
-- CC regs are saved to a scratch register instead of stack.
-- All regs used by a instruction are now recorded in MachineInstr::regsUsed,
since regs used to save values *across* an instruction are not obvious
either from the operands or from the LiveVar sets.
-- An (explicit or implicit) operand may now be both a def and a use.
This is needed for conditional move operations.
So an operand may need spill code both before and after the instruction.
Other changes:
-- Added several get{Class,Type} functions.
-- Added unified-to-local register number conversion.
-- class MachineCodeForBasicBlock is now an annotation on BasicBlock.
-- Suggest/Color methods may modify the MachineInstr (and always did),
so don't make that argument const!
-- Caller-saving code doesn't need its special purpose code for
handling CC registers since cpMem<->Reg handle those correctly now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2834 91177308-0d34-0410-b5e6-96231b3b80d8
handle conditional move instructions:
-- cpMem<->Reg functions now support CC registers (int and FP) correctly.
-- Scratch registers must be explicitly provided to cpMem<->Reg when
needed, since CC regs need one to be copied to/from memory.
-- CC regs are saved to a scratch register instead of stack.
-- All regs used by a instruction are now recorded in MachineInstr::regsUsed,
since regs used to save values *across* an instruction are not obvious
either from the operands or from the LiveVar sets.
-- An (explicit or implicit) operand may now be both a def and a use.
This is needed for conditional move operations.
So an operand may need spill code both before and after the instruction.
-- class MachineCodeForBasicBlock is now an annotation on BasicBlock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2833 91177308-0d34-0410-b5e6-96231b3b80d8
because operands may be modified directly to set register.
Also, class MachineCodeForBasicBlock is now an annotation on BasicBlock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2832 91177308-0d34-0410-b5e6-96231b3b80d8
so additional dep. edges have to be added.
This was needed to correctly handle conditional move instructions!
MachineCodeForBasicBlock is now an annotation on BasicBlock.
Renamed "earliestForNode" to "earliestReadyTimeForNode".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2826 91177308-0d34-0410-b5e6-96231b3b80d8
