Commit Graph

20165 Commits

Author SHA1 Message Date
Tom Stellard
1f67c63cb2 DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:55:03 +00:00
Tom Stellard
8ea83d4999 R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
These are really the same address space in hardware.  The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access.  When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:54:56 +00:00
Manman Ren
7894ffd006 Debug Info: improve the Finder.
Improve the Finder to handle context of a DIVariable.
If Scope is a DICompileUnit, add it to the list of CUs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187003 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 23:10:00 +00:00
Quentin Colombet
17f99a991f [ARM][ISel] Improve the lowering of vector loads.
When vectors are built from a single value, the ARM lowering issues a
scalar_to_vector node.
This node is then always morphed into a move from the general purpose unit to
the vector unit.
When the value comes from a load, this can be simplified into a vector load to
the right lane.

This patch changes the lowering of insert_vector_elt to expose a vector
friendly pattern in this situation.

This is a step toward fixing <rdar://problem/14170854>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186999 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 22:34:47 +00:00
Rafael Espindola
113034596c Add not so that these tests pass with pipefail enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 13:18:20 +00:00
Rafael Espindola
810cdaf763 Add -disable-debug-info-verifier.
Found while testing with pipefail enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186937 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 12:31:37 +00:00
Rafael Espindola
26b10da9c2 Add an initial implementation of archive symbol table generation.
The symbol table has forward references in the file. Instead of allocating
a temporary buffer or counting the size and then writing, this implementation
writes a dummy value first and patches it once the final value is known.

There is room for performance improvement. I will implement them as soon as I
get some other features (like a ranlib mode) in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186934 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 10:47:01 +00:00
NAKAMURA Takumi
325a8dcc9d llvm/test/DebugInfo/X86/dbg-value-range.ll: Add -disable-debug-info-verifier, too, since r186902.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:41:51 +00:00
Craig Topper
9b8b830f3f Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:50:47 +00:00
Tom Stellard
10205d5a73 R600: Add support for 24-bit MAD instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186923 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:49 +00:00
Tom Stellard
3f5d63b956 R600: Add support for 24-bit MUL instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:42 +00:00
Tom Stellard
eb643b9b37 R600: Improve support for < 32-bit loads
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:35 +00:00
Tom Stellard
58d3335cb9 R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()
This increases the number of opportunites we have for folding.  With the
previous implementation we were unable to fold into any instructions
other than the first when multiple instructions were selected from a
single SDNode.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186919 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:24 +00:00
Tom Stellard
a7eea0568c R600: Use KCache for kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:18 +00:00
Tom Stellard
f502c292f6 R600: Use the same compute kernel calling convention for all GPUs
A side-effect of this is that now the compiler expects kernel arguments
to be 4-byte aligned.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186916 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:48:05 +00:00
Tom Stellard
5864284d71 R600: Use correct LoadExtType when lowering kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186915 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:47:58 +00:00
Tom Stellard
2bb20fd2bf R600: Clean up extended load patterns
Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186914 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:47:52 +00:00
Tom Stellard
d7a472c9c6 R600: Expand vector FNEG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:47:46 +00:00
Manman Ren
0e29eeec27 Debug Info Finder: use processDeclare and processValue to list debug info
MDNodes used by DbgDeclareInst and DbgValueInst.

Another 16 testing cases failed and they are disabled with
-disable-debug-info-verifier.
A total of 34 cases are disabled with -disable-debug-info-verifier and will be
corrected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 00:22:51 +00:00
Nadav Rotem
62657090de When we vectorize across multiple basic blocks we may vectorize PHINodes that create a cycle. We already break the cycle on phi-nodes, but arithmetic operations are still uplicated. This patch adds code that checks if the operation that we are vectorizing was vectorized during the visit of the operands and uses this value if it can.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186883 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 22:18:07 +00:00
Kevin Enderby
877d123bdb Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 21:25:31 +00:00
Jakub Staszak
2b6427335d Fix typo in test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 21:10:42 +00:00
Craig Topper
4e3170b63a Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 20:46:37 +00:00
Bill Wendling
0dcba2fadb Recommit r186217 with testcase fix:
Use the function attributes to pass along the stack protector buffer size.

 Now that we have robust function attributes, don't use a command line option to
 specify the stack protecto buffer size.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 20:15:21 +00:00
Akira Hatanaka
9a05b98ef9 [mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186861 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 19:30:38 +00:00
Rafael Espindola
30115ec7a3 Mark ELF's first symbol as format specific so that llvm-nm ignores it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186860 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 19:24:34 +00:00
Akira Hatanaka
0b92642767 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 18:52:22 +00:00
Mihai Popa
0226538292 This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 15:49:36 +00:00
Rafael Espindola
51392a079e Replace archive members in the old position.
This matches gnu archive behavior and since archive member order can change
which member is used, not changing the order on replacement looks like the
right thing to do.

This patch also refactors the logic for which archive member to keep and
whether to move it to a helper function (computeInsertAction). The
nesting in computeNewArchiveMembers was getting a bit confusing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 15:11:51 +00:00
Rafael Espindola
bb8234b7ff Don't depend on a llvm-ar specific behavior.
GNU ar when not given the a or b modifiers replaces archive members in the
same location of the old ones. I am about to implement that in llvm-ar. For
now, just don't depend on the current llvm-ar behavior on this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 12:41:04 +00:00
Justin Holewinski
3a8ee4ffd7 [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append
.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-22 12:18:04 +00:00
Richard Smith
72c8331ec1 Treat nothrow forms of ::operator delete and ::operator delete[] as
deallocation functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-21 23:11:42 +00:00
Rafael Espindola
02a1364bf8 Handle replacement into a position past the original member.
We were incorrectly computing where to insert a member if it was replacing
a previous member that was before the insert point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-21 12:58:07 +00:00
Rafael Espindola
64f2f910bd Don't crash when llvm.compiler.used becomes empty.
GlobalOpt simplifies llvm.compiler.used by removing any members that are also
in the more strict llvm.used. Handle the special case where llvm.compiler.used
becomes empty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-20 23:33:15 +00:00
Matt Arsenault
5f53c3be6f Disallow global aliases to bitcast between address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-20 17:46:05 +00:00
Stephen Lin
a98ce503b9 InstCombine: call FoldOpIntoSelect for all floating binops, not just fmul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-20 07:13:13 +00:00
Matt Arsenault
ff29d235ed Have InlineCost check constant fcmps
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-20 04:09:00 +00:00
Lang Hames
7b61a70193 Refactor AnalyzeBranch on ARM. The previous version did not always analyze
indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.

This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.

For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll). 

<rdar://problem/14464830>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 23:52:47 +00:00
Rui Ueyama
2f6c0484d6 Retry submitting r186623: COFFDumper: Dump data directory entries.
The original change was rolled back in r186627 because of test
failures on the big endian machine. I believe I fixed the issue
so re-submitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 23:23:29 +00:00
Vincent Lejeune
272458bd06 R600: Don't emit empty then clause and use alu_pop_after
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 21:45:15 +00:00
Rafael Espindola
b55dcfe47f Fix inserting new elements in a specified location.
We were only handling the 'a' and 'b' options during moves before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186721 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 21:23:28 +00:00
Rafael Espindola
7096831971 s/compiler_used/compiler.used/.
We were incorrectly using compiler_used instead of compiler.used. Unfortunately
the passes using the broken name had tests also using the broken name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 18:44:51 +00:00
Richard Sandiford
6dae7ae765 [SystemZ] Add tests for ALHSIK and ALGHSIK
The insn definitions themselves crept into r186689, sorry.
This should be the last of the distinct-ops instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:44:32 +00:00
Richard Sandiford
c7c7e1502a [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186689 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:37:00 +00:00
Joey Gouly
6fec715a1a [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:34:16 +00:00
Richard Sandiford
70d3e71f2e [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186687 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:32:12 +00:00
Richard Sandiford
dc05e0bff6 [SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:26:39 +00:00
Richard Sandiford
52b2774577 [SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186685 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:24:22 +00:00
Richard Sandiford
db92fb0716 [SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:21:55 +00:00
Tilmann Scheller
cae5d5ea65 ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:18:56 +00:00