Commit Graph

70 Commits

Author SHA1 Message Date
Alexey Samsonov
60a82bcf13 Fix left shifts of negative values in MipsDisassembler.
This bug was reported by UBSan.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-02 17:49:16 +00:00
NAKAMURA Takumi
9d8661d666 Prune dependency to MC from each target disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213856 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 11:45:11 +00:00
NAKAMURA Takumi
9fda421ee4 Update library dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213832 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 02:10:42 +00:00
Daniel Sanders
543f70b040 [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64 moves
Summary:
This is similar to r210771 which did the same thing for MTHC1.

Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the
wrong definitions.

Differential Revision: http://reviews.llvm.org/D4483


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212936 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 12:41:31 +00:00
Zoran Jovanovic
f3a4a4bb56 [mips][mips64r6] Add BLTC and BLTUC instructions
Differential Revision: http://reviews.llvm.org/D3923


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211167 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-18 14:36:00 +00:00
Daniel Sanders
af0d72a6f9 [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
Summary:
The linked-load, store-conditional operations have been re-encoded such
that have a 9-bit offset instead of the 16-bit offset they have prior to
MIPS32r6/MIPS64r6.

While implementing this, I noticed that the atomic load/store pseudos always
emit a sign extension using sll and sra. I have improved this to use seb/seh
when they are available (MIPS32r2/MIPS64r2 and above).

Depends on D4118

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-16 13:13:03 +00:00
Daniel Sanders
7cfd0ffb3b [mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:15:59 +00:00
Daniel Sanders
8007133f3e [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6
Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 13:39:06 +00:00
Zoran Jovanovic
24ba4fa9e1 [mips][mips64r6] Add bgec and bgeuc instructions
Differential Revision: http://reviews.llvm.org/D4017


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210770 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-12 11:47:44 +00:00
Zoran Jovanovic
0c7ac480e2 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 09:49:51 +00:00
Daniel Sanders
c96096cc0f [mips][mips64r6] Add b[on]vc
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
  * Also made non-functional change to DecodeBranchTarget and
    DecodeBranchTargetMM to keep implementation style consistent between
    them.
* Difficult encodings are handled by a custom decode method on the most
  general encoding in the group. This method will convert the MCInst to a
  different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:23:21 +00:00
Daniel Sanders
820861536c [mips][mips64r6] Add bc[12](eq|ne)z
Summary: Depends on D3691

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 12:56:39 +00:00
Zoran Jovanovic
b8c3bcbbfa [mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208974 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 11:03:45 +00:00
Daniel Sanders
06961bf147 [mips][mips64r6] Add addiupc, aluipc, and auipc
Summary:
No support for symbols in place of the immediate yet since it requires new
relocations.

Depends on D3671

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3689

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 10:45:58 +00:00
Craig Topper
91b10fb0e9 [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207506 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 07:58:02 +00:00
Chandler Carruth
283b399377 [Modules] Make Support/Debug.h modular. This requires it to not change
behavior based on other files defining DEBUG_TYPE, which means it cannot
define DEBUG_TYPE at all. This is actually better IMO as it forces folks
to define relevant DEBUG_TYPEs for their files. However, it requires all
files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't
already. I've updated all such files in LLVM and will do the same for
other upstream projects.

This still leaves one important change in how LLVM uses the DEBUG_TYPE
macro going forward: we need to only define the macro *after* header
files have been #include-ed. Previously, this wasn't possible because
Debug.h required the macro to be pre-defined. This commit removes that.
By defining DEBUG_TYPE after the includes two things are fixed:

- Header files that need to provide a DEBUG_TYPE for some inline code
  can do so by defining the macro before their inline code and undef-ing
  it afterward so the macro does not escape.

- We no longer have rampant ODR violations due to including headers with
  different DEBUG_TYPE definitions. This may be mostly an academic
  violation today, but with modules these types of violations are easy
  to check for and potentially very relevant.

Where necessary to suppor headers with DEBUG_TYPE, I have moved the
definitions below the includes in this commit. I plan to move the rest
of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big
enough.

The comments in Debug.h, which were hilariously out of date already,
have been updated to reflect the recommended practice going forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 22:55:11 +00:00
Lang Hames
508bd63046 [MC] Require an MCContext when constructing an MCDisassembler.
This patch re-introduces the MCContext member that was removed from
MCDisassembler in r206063, and requires that an MCContext be passed in at
MCDisassembler construction time. (Previously the MCContext member had been
initialized in an ad-hoc fashion after construction). The MCCContext member
can be used by MCDisassembler sub-classes to construct constant or
target-specific MCExprs.

This patch updates disassemblers for in-tree targets, and provides the
MCRegisterInfo instance that some disassemblers were using through the
MCContext (previously those backends were constructing their own
MCRegisterInfo instances).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 04:40:56 +00:00
NAKAMURA Takumi
6c5bb2e764 LLVMBuild.txt: Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205961 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 11:16:17 +00:00
Daniel Sanders
bd48d31b37 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-01 10:35:28 +00:00
Daniel Sanders
1c056d8be9 Revert: [mips] Rewrite MipsAsmParser and MipsOperand.' due to buildbot errors in lld tests.
It's currently unable to parse 'sym + imm' without surrounding parenthesis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 18:51:43 +00:00
Daniel Sanders
8f7dc89e21 [mips] Rewrite MipsAsmParser and MipsOperand.
Summary:
Highlights:
- Registers are resolved much later (by the render method).
  Prior to that point, GPR32's/GPR64's are GPR's regardless of register
  size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register
  size or FR mode. Numeric registers can be anything.
- All registers are parsed the same way everywhere (even when handling
  symbol aliasing)
  - One consequence is that all registers can be specified numerically
    almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing
    but that can be easily resolved.
- Removes the need for the hasConsumedDollar hack
- Parenthesis and Bracket suffixes are handled generically
- Micromips instructions are parsed directly instead of going through the
  standard encodings first.
- rdhwr accepts all 32 registers, and the following instructions that previously
  xfailed now work:
    ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d,
    c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1
- Diagnostics involving registers point at the correct character (the $)
- There's only one kind of immediate in MipsOperand. LSA immediates are handled
  by the predicate and renderer.

Lowlights:
- Hardcoded '$zero' in the div patterns is handled with a hack.
  MipsOperand::isReg() will return true for a k_RegisterIndex token
  with Index == 0 and getReg() will return ZERO for this case. Note that it
  doesn't return ZERO_64 on isGP64() targets.
- I haven't cleaned up all of the now-unused functions.
  Some more of the generic parser could be removed too (integers and relocs
  for example).
- insve.df needed a custom decoder to handle the implicit fourth operand that
  was needed to make it parse correctly. The difficulty was that the matcher
  expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-31 17:43:46 +00:00
Yaron Keren
b62b44ccc5 Cleaning up a bunch of pre-Visual C++ 2012 build hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 09:23:33 +00:00
Zoran Jovanovic
2a80d7db79 Fixed operand of SC microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:22:56 +00:00
Matheus Almeida
4faa2b38fb [mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded.
In more detail, immediate fields of LD/ST instructions should be
divided/multiplied by the size of the data format before encoding and
after decoding, respectively.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-05 11:06:22 +00:00
NAKAMURA Takumi
ad363187c4 [CMake] Let add_public_tablegen_target responsible to provide dependency to CommonTableGen.
add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS.
LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 17:04:04 +00:00
NAKAMURA Takumi
9ec9b8434b [CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() sets them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195921 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28 14:53:30 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 14:53:22 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:38:59 +00:00
Matheus Almeida
348da8d6b5 [mips][msa] Direct Object Emission support for LD/ST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 13:07:13 +00:00
Matheus Almeida
006cff8d7b [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA.
These instructions are logically related as they allow read/write of MSA control registers.
Currently MSA control registers are emitted by number but hopefully that will change as soon 
as GAS starts accepting them by name as that would make the assembly easier to read.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-21 12:26:50 +00:00
Jack Carter
9fa81ab838 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-26 00:09:46 +00:00
Jack Carter
42d9ca6299 [mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-25 23:50:44 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:30:36 +00:00
Akira Hatanaka
a796d90c0e [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:55:15 +00:00
Akira Hatanaka
3531db14c6 [mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 22:58:56 +00:00
Akira Hatanaka
7d6355226c [mips] Rename DSPRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:53:38 +00:00
Akira Hatanaka
cbaf6d0cc3 [mips] Rename HIRegs and LORegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-14 00:47:08 +00:00
Akira Hatanaka
491d04969d [mips] Rename accumulator register classes and FP register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
David Blaikie
040ef013ac Remove unused functions introduced in r172685 to unbreak the Clang -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-07 00:25:12 +00:00
Akira Hatanaka
1858786285 [mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Benjamin Kramer
bc2160f7c9 Stop leaking register infos in the disassemblers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-03 22:16:16 +00:00
Akira Hatanaka
83d8ef133b [mips] Fix FP branch instructions to have explicit FP condition code register
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:13:47 +00:00
Vladimir Medic
ab42fc66b1 Fixing a buildbot failure:unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 11:43:20 +00:00
Chad Rosier
096c0a0331 [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 22:23:32 +00:00
Benjamin Kramer
49a6a8d8f2 Remove the Copied parameter from MemoryObject::readBytes.
There was exactly one caller using this API right, the others were relying on
specific behavior of the default implementation. Since it's too hard to use it
right just remove it and standardize on the default behavior.

Defines away PR16132.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-24 10:54:58 +00:00
Akira Hatanaka
26aef5b7d6 [mips] DSP-ASE move from HI/LO register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18 00:52:44 +00:00
Akira Hatanaka
2c2c33a167 [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 01:58:00 +00:00
Reed Kotler
38f85c5b9f Remove the form field from Mips16 instruction formats and set things
up so that we can apply the direct object emitter patch. This patch
should be a nop right now and it's test is to not break what is already
there.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-14 03:05:25 +00:00
Jack Carter
e11dda8631 This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Formatting fixes. Mostly long lines and 
blank spaces at end of lines.

Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-19 02:00:40 +00:00