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Commit Graph

Author	SHA1	Message	Date
Frederic Riss	1638ca5493	Fix some unnoticed/unwanted behavior change from r222319. The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228109 91177308-0d34-0410-b5e6-96231b3b80d8	2015-02-04 03:10:03 +00:00
Saleem Abdulrasool	8f9108459e	aarch64: support target-specific .req assembler directive Based on the support for .req on ARM. The aarch64 variant has to keep track if the alias register was a vector register (v0-31) or a general purpose or VFP/Advanced SIMD ([bhsdq]0-31) register. Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212161 91177308-0d34-0410-b5e6-96231b3b80d8	2014-07-02 04:50:23 +00:00

Author

SHA1

Message

Date

Frederic Riss

1638ca5493

Fix some unnoticed/unwanted behavior change from r222319.

The ARM assembler allows register alias redefinitions as long as it
targets the same register. r222319 broke that. In the AArch64 case
it would just produce a new warning, but in the ARM case it would
error out on previously accepted assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228109 91177308-0d34-0410-b5e6-96231b3b80d8

2015-02-04 03:10:03 +00:00

Saleem Abdulrasool

8f9108459e

aarch64: support target-specific .req assembler directive

Based on the support for .req on ARM. The aarch64 variant has to keep track if
the alias register was a vector register (v0-31) or a general purpose or
VFP/Advanced SIMD ([bhsdq]0-31) register.

Patch by Janne Grunau!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212161 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-02 04:50:23 +00:00

2 Commits