Owen Anderson
d94b6a16fe
Move some more functionality from MRegisterInfo to TargetInstrInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-04 23:57:37 +00:00
Owen Anderson
f6372aa1cc
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 21:11:32 +00:00
Chris Lattner
4ee451de36
Remove attribution from file headers, per discussion on llvmdev.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
Evan Cheng
d64b5c82b9
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
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the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-05 03:14:33 +00:00
Evan Cheng
aee4af68ae
Remove redundant foldMemoryOperand variants and other code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-02 08:30:39 +00:00
Evan Cheng
e62f97c094
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-01 02:07:52 +00:00
Dale Johannesen
b97aec663b
Add parameter to getDwarfRegNum to permit targets
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to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-13 19:13:01 +00:00
Anton Korobeynikov
f191c80cd7
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11 19:50:10 +00:00
Dale Johannesen
483ec21d90
Interchange Dwarf numbers of ESP and EBP on x86 Darwin.
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Much improvement in exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43794 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-07 00:25:05 +00:00
Evan Cheng
db807edd66
Use movups to spill / restore SSE registers on targets where stacks alignment is
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less than 16. This is a temporary solution until dynamic stack alignment is
implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43703 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-05 07:30:01 +00:00
Evan Cheng
66f7163545
Local spiller optimization:
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Turn a store folding instruction into a load folding instruction. e.g.
xorl %edi, %eax
movl %eax, -32(%ebp)
movl -36(%ebp), %eax
orl %eax, -32(%ebp)
=>
xorl %edi, %eax
orl -36(%ebp), %eax
mov %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43192 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-19 21:23:22 +00:00
Evan Cheng
f0a0cddbcd
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
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- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18 22:40:57 +00:00
Evan Cheng
58184e6878
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18 21:29:24 +00:00
Christopher Lamb
91ee18c1f7
Fix a typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43144 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18 19:28:55 +00:00
Evan Cheng
106e8020bd
Change unfoldMemoryOperand(). User is now responsible for passing in the
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register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42946 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-13 02:35:06 +00:00
Evan Cheng
75b4e46b8a
Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42624 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05 01:34:55 +00:00
Evan Cheng
7f3394f379
Refactor code to add load / store folded instructions -> register only
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instructions reverse map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42509 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-01 23:44:33 +00:00
Evan Cheng
ff11026575
- Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from).
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- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42372 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-26 21:31:07 +00:00
Evan Cheng
9efce638d3
Allow copyRegToReg to emit cross register classes copies.
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Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-26 06:25:56 +00:00
Evan Cheng
f4c3a59dba
Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41599 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 05:54:07 +00:00
Duncan Sands
ee46574931
Move getX86RegNum into X86RegisterInfo and use it
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in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41577 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-29 19:01:20 +00:00
Evan Cheng
64d80e3387
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Evan Cheng
7e7bbf8271
Only adjust esp around calls in presence of alloca.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40028 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 00:42:05 +00:00
Evan Cheng
89d1659cf2
Use push / pop for prologues and epilogues.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39967 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-17 07:59:08 +00:00
Anton Korobeynikov
2365f51ed0
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-14 14:06:15 +00:00
Evan Cheng
97de913821
eliminateFrameIndex() change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 09:13:03 +00:00
Evan Cheng
bf2c8b3c96
Added MRegisterInfo hook to re-materialize an instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20 08:09:38 +00:00
Evan Cheng
5e6df4647e
PEI now passes a RegScavenger ptr to eliminateFrameIndex.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-28 00:21:17 +00:00
Jim Laskey
62819f3144
Support to provide exception and selector registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-21 22:54:50 +00:00
Evan Cheng
b371f457b0
Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-19 21:49:54 +00:00
Reid Spencer
a284cbf667
For PR1207:
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Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-19 03:20:00 +00:00
Evan Cheng
eceada6728
Added getReservedRegs().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17 11:06:00 +00:00
Jim Laskey
0e41094d49
Call frames for intel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33490 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-24 19:15:24 +00:00
Evan Cheng
dc77540d95
hasFP() is now a virtual method of MRegisterInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-23 00:57:47 +00:00
Evan Cheng
c2b861da18
Fix naming inconsistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32823 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-02 21:33:40 +00:00
Jeff Cohen
d41b30def3
Unbreak VC++ build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31464 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-05 19:31:28 +00:00
Evan Cheng
25ab690a43
Committing X86-64 support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 06:48:29 +00:00
Chris Lattner
2926869b4a
Fix a long-standing wart in the code generator: two-address instruction lowering
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30108 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05 02:12:02 +00:00
Evan Cheng
0f3ac8d8d4
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-18 00:12:58 +00:00
Evan Cheng
8f7f7125e9
Better implementation of truncate. ISel matches it to a pseudo instruction
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that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28119 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-05 05:40:20 +00:00
Jim Laskey
4188699f80
Foundation for call frame information.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27491 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-07 16:34:46 +00:00
Jim Laskey
a99791886d
Expose base register for DwarfWriter. Refactor code accordingly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 13:48:33 +00:00
Jim Laskey
f1d78e8335
Add support to locate local variables in frames (early version.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 18:12:57 +00:00
Chris Lattner
4083960147
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 20:12:32 +00:00
Chris Lattner
1d6ecd03ea
add a method
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25910 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 19:57:16 +00:00
Chris Lattner
97d5e6461a
Pass extra regclasses into spilling code
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-30 01:29:42 +00:00
Chris Lattner
a92aab74dd
Implement the isLoadFromStackSlot interface
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23387 91177308-0d34-0410-b5e6-96231b3b80d8
2005-09-19 05:23:44 +00:00
Chris Lattner
2505d6b727
The simple isel being gone makes this dead!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22914 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:32:03 +00:00
Misha Brukman
0e0a7a45d3
* Remove trailing whitespace
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* Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21426 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-21 23:38:14 +00:00
Chris Lattner
01d0efba39
Code insertion methods now return void instead of an int.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15780 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-15 22:15:11 +00:00