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22c687b642
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2518 Commits

Author SHA1 Message Date
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 02:13:41 +00:00
Evan Cheng
7f68719517 Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-14 00:21:45 +00:00
Evan Cheng
c4ca40eb5e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103731 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 20:02:08 +00:00
Bob Wilson
1190c14b54 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. 
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 19:58:24 +00:00
Daniel Dunbar
1860e7dcfd Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 03:19:36 +00:00
Evan Cheng
69b9f9883e Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103692 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 01:12:06 +00:00
Evan Cheng
d929f77738 Expand VMOVQQ into a pair of VMOVQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103684 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:17:02 +00:00
Evan Cheng
020cc1b4d0 Mark some pattern-less instructions as neverHasSideEffects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103683 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-13 00:16:46 +00:00
Evan Cheng
431300797b Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103667 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 23:13:12 +00:00
Evan Cheng
a4d73d01c4 Remove a dead fixme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103642 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 20:20:22 +00:00
Rafael Espindola
18c1021ec1 Add support for movi32 of global values to the new (MC) asm printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 05:16:34 +00:00
Evan Cheng
5bdc2aa264 vst instructions are modeled as this: 
v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-12 01:42:50 +00:00
Evan Cheng
9647f3d981 Avoid breaking vstd when reg_sequence is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 21:07:36 +00:00
Duncan Sands
16d8f8bd91 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 20:16:09 +00:00
Dan Gohman
ff7a562751 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 17:31:57 +00:00
Dan Gohman
419e4f9263 Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 16:21:03 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Evan Cheng
0ce537a9db Model some vst3 and vst4 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 01:19:40 +00:00
Evan Cheng
e9e2ba05de Model some vld3 instructions with REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 21:26:24 +00:00
Evan Cheng
603afbfe2a Model vld2 / vst2 with reg_sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-10 17:34:18 +00:00
Jim Grosbach
4b77f6a85a Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 18:34:55 +00:00
Evan Cheng
435d499177 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 02:04:02 +00:00
Evan Cheng
07a6d9391c Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 01:54:08 +00:00
Evan Cheng
c10b5afbe8 Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103218 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-07 00:24:52 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 20:33:48 +00:00
Evan Cheng
746ad69e08 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 19:06:44 +00:00
Bob Wilson
429009b0f1 Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 16:05:26 +00:00
Jim Grosbach
d31f00b7f7 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103181 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 15:32:49 +00:00
Shantonu Sen
eae216c6d3 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 14:57:47 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 06:36:08 +00:00
Dan Gohman
1ef7c82128 Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 05:08:57 +00:00
Eric Christopher
f865cb5c1f Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 02:29:06 +00:00
Evan Cheng
9c35ee2099 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:54:03 +00:00
Evan Cheng
4ffc22ae00 Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:52:03 +00:00
Evan Cheng
d31c5496d7 Cosmetic changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:34:11 +00:00
Evan Cheng
7f2f436267 storeRegToStackSlot has forgotten about QPR_8 register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103154 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-06 01:32:54 +00:00
Jim Grosbach
29402132f3 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 23:44:43 +00:00
Evan Cheng
676b2dfd27 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 22:15:40 +00:00
Jim Grosbach
b1dc393bd5 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 20:44:35 +00:00
Evan Cheng
de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-05 18:28:36 +00:00
Evan Cheng
94cc6d3a2b With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:39:49 +00:00
Evan Cheng
826bdfa603 Do not pre-allocate for registers which form a REG_SEQUENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 20:38:12 +00:00
Jim Grosbach
6e62b4ef14 rdar://7937137 - dbg values not being handled in thumb1 version of 
eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-04 00:11:37 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-01 00:01:06 +00:00
Evan Cheng
8601a3d4de Frame index can be negative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-29 01:13:30 +00:00
Jim Grosbach
d100755bab Add sizes non-floating point versions for the eh sjlj intrinsic expansions. 
rdar://7895451



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102526 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-28 20:33:09 +00:00
Bob Wilson
5dfa87ecc6 Handle register-to-register copies within the tGPR class. 
Radar 7896289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 23:20:08 +00:00
Dale Johannesen
3f282aa94b Handle target-specific form of DBG_VALUE in AsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 20:07:31 +00:00
Evan Cheng
62b50656ce Add ARM specific emitFrameIndexDebugValue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-26 07:39:25 +00:00
Jim Grosbach
3a1287b470 Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 
extraction. This fixes PR5998.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-22 23:24:18 +00:00