Commit Graph

96 Commits

Author SHA1 Message Date
Simon Atanasyan
f132bf39b9 [Mips] Add more SHF_MIPS_xxx ELF section flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 20:41:45 +00:00
Zoran Jovanovic
1aaf43c2a2 Support for microMIPS jump instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29 16:38:59 +00:00
Zonr Chang
5e4d8a5eca Include missing Compiler.h for using LLVM_ENUM_INT_TYPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-24 08:17:39 +00:00
Zoran Jovanovic
0082717cb5 Support for microMIPS relocations 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-23 16:14:44 +00:00
Simon Atanasyan
26ba5df2eb [Mips] Add MIPS program header types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-06 08:49:41 +00:00
Reid Kleckner
118a0659ab Explicitly request unsigned enum types when desired
The underlying type of all plain enums in MSVC is 'int', even if the
enumerator contains large 32-bit unsigned values or values greater than
UINT_MAX.  The only way to get a large or unsigned enum type is to
request it explicitly with the C++11 strong enum types feature.

However, since LLVM isn't C++11 yet, I had to add a conditional
LLVM_ENUM_INT_TYPE to Compiler.h to control its usage.

The motivating true positive for this change is compiling PointerIntPair
with MSVC for win64.  The PointerIntMask value is supposed to be pointer
sized value of all ones with some low zeros.  Instead, it's truncated to
32-bits!  We are only saved later because it is sign extended back in
the AND with int64_t, and we happen to want all ones.

This silences lots of -Wmicrosoft warnings during a clang self-host
targeting Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-23 23:26:57 +00:00
Benjamin Kramer
766f25306a ELF: Add support for the exclude section bit for gas compat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 19:53:20 +00:00
Rafael Espindola
6fccaafd8b Remove the mblaze backend from llvm.
Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 18:55:05 +00:00
Akira Hatanaka
3af1c9d334 [mips] Use pristine object file while processing relocations.
Similar to ARM change r182800, dynamic linker will read bits/addends from
    the original object rather than from the object that might have been patched
    previously. For the purpose of relocations for MCJIT stubs on MIPS, we
    internally use otherwise unused MIPS relocations.
    
    The change also enables MCJIT unit tests for MIPS (EL/BE), and the following
    two tests now pass:
    
    - MCJITTest.return_global and
    - MCJITTest.multiple_functions.
    
    These issues have been tracked as Bug 16250.

    Patch by Petar Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 01:58:40 +00:00
Ulrich Weigand
228e0afcfd [PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 23:33:29 +00:00
Ulrich Weigand
bbeba2c200 [PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 22:27:57 +00:00
Ulrich Weigand
5de735a962 [PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers.  Used by the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 16:49:50 +00:00
Ulrich Weigand
84569698f0 [PowerPC] Support R_PPC_REL16 family of relocations
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:

  li 1, base-.

This patch adds support for those relocation types in the assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 14:44:37 +00:00
Ulrich Weigand
cab0a19338 [PowerPC] Support various tls-related modifiers
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code.  This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 14:44:15 +00:00
Ulrich Weigand
f7c1ee79fe [PowerPC] Support @higher et.al. modifiers
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 14:43:42 +00:00
Ulrich Weigand
f8f87dcfce [PowerPC] Support @toc@h modifier
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-21 14:43:10 +00:00
Sean Silva
d56d756611 [ELF] Add ELFOSABI_GNU.
ELFOSABI_LINUX is a historical alias for ELFOSABI_GNU according to
<http://www.sco.com/developers/gabi/latest/ch4.eheader.html>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:55:58 +00:00
Simon Atanasyan
e4ee452576 [Mips] Add Mips specific dynamic table entry tags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-28 20:48:56 +00:00
Ulrich Weigand
c37077af7b [PowerPC] Add some missing PPC64 relocs
All R_PPC_... relocs should also be present (using the same number)
under the corresponding R_PPC64_... name.   The latter were missing
for a couple of cases, which this patch adds.

This is not a big problem when emitting the reloc, because we can
just use the R_PPC_... define instead.  But it is a problem when
*dumping* relocations e.g. using llvm-readobj, because this will
expect only R_PPC64_... values when inspecting a ppc64 ELF file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-08 17:50:57 +00:00
Richard Sandiford
820b3fd771 [SystemZ] Add ELF relocation support
Another step towards reinstating the SystemZ backend.  Tests will be
included in the main backend patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-03 11:11:15 +00:00
Nico Rieck
a6cd815994 Add missing relocation names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12 04:01:28 +00:00
Ulrich Weigand
65e90c0364 PowerPC: Simplify handling of fixups.
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like:

 if (isSVR4ABI() && is64BitMode())
   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_toc16));
 else
   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_lo16));

This is a problem for the asm parser, since it requires knowledge of
the ABI / 64-bit mode to be set up.  However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.

Fortunately, this is actually completely unnecessary; that code was added
to decide whether to generate TOC relocations, but that information is in
fact already encoded in the VariantKind of the underlying symbol.

This commit therefore merges those fixup types into one, and then decides
which relocation to use based on the VariantKind.

No changes in generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 10:56:47 +00:00
Joerg Sonnenberger
4bf030402d Add two of the float related ARM-specific entries for e_flags needed for
linkers to interact with GNU ld.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 08:01:36 +00:00
Bill Schmidt
fc7695a653 Fix missing relocation for TLS addressing peephole optimization.
Report and fix due to Kai Nacke.  Testcase update by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-25 16:44:35 +00:00
Jack Carter
5cdeca8b1d ELF symbol table field st_other support,
excluding visibility bits.

Mips (o32 abi) specific e_header setting.

EF_MIPS_ABI_O32 needs to be set in the 
ELF header flags for o32 abi output.

Contributer: Reed Kotler


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 22:29:00 +00:00
Jack Carter
c989c61798 ELF symbol table field st_other support,
excluding visibility bits.

Mips (Mips16) specific e_header setting.

EF_MIPS_ARCH_ASE_M16 needs to be set in the 
ELF header flags for Mips16.

Contributer: Reed Kotler


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 22:14:34 +00:00
Jack Carter
ccb3c9c270 ELF symbol table field st_other support,
excluding visibility bits.

Mips (MicroMips) specific STO handling .

The st_other field settig for STO_MIPS_MICROMIPS

Contributer: Zoran Jovanovic




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 22:04:37 +00:00
Michael J. Spencer
6d3a278aab [ELF] Add STN_UNDEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 01:56:36 +00:00
Jack Carter
dc08bfbd56 This patch just fixes up various llvm formatting
violations such as tabs, blanks at eol and long 
lines.


 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-12 21:29:39 +00:00
Jack Carter
7304702ef9 This patch that sets the Mips ELF header flag for
MicroMips architectures. 

Contributer: Zoran Jovanovic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 09:30:03 +00:00
Tim Northover
72062f5744 Add AArch64 as an experimental target.
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.

This initial commit should have support for:
    + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
      (except the late addition CRC instructions).
    + CodeGen features required for C++03 and C99.
    + Compilation for the "small" memory model: code+static data <
      4GB.
    + Absolute and position-independent code.
    + GNU-style (i.e. "__thread") TLS.
    + Debugging information.

The principal omission, currently, is performance tuning.

This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.

Further reviews would be gratefully received.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31 12:12:40 +00:00
Jack Carter
97130e2b3d This patch implements runtime ARM specific
setting of ELF header e_flags.

Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30 02:24:33 +00:00
Michael J. Spencer
e35badad22 [ELF] Add R_X86_64_IRELATIVE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173316 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24 02:08:25 +00:00
Tim Northover
318b2cc86f Fix truncation of relocation types in Support/ELF.h
This is a follow-up to r171845, which fixes the same issue in the Support code.
Only targets with >256 relocations (principally AArch64) should be affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 12:01:43 +00:00
Jack Carter
c91cbb9b0c This is a resubmittal. For some reason it broke the bots yesterday
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.
Support for Mips register information sections.

Mips ELF object files have a section that is dedicated
to register use info. Some of this information such as
the assumed Global Pointer value is used by the linker
in relocation resolution.

The register info file is .reginfo in o32 and .MIPS.options
in 64 and n32 abi files.

This patch contains the changes needed to create the sections,
but leaves the actual register accounting for a future patch.


Contributer: Jack Carter
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-18 21:20:38 +00:00
Adhemerval Zanella
a1db5de9e7 PowerPC: EH adjustments
This patch adjust the r171506 to make all DWARF enconding pc-relative
for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT
(since the eh_frame will not generate PIC-relative relocation) and also
adds the emission of stubs created by the TTypeEncoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171979 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 17:08:15 +00:00
Shankar Easwaran
cde8168964 add hexagon flags in ELF.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171977 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-09 16:34:46 +00:00
Adhemerval Zanella
7b449889e7 PowerPC: Fix eh_frame relocation for PIC
This patch fixes the PPC eh_frame definitions for the personality and 
frame unwinding for PIC objects. It makes PIC build correctly creates
relative relocations in the '.rela.eh_frame' segments and thus avoiding
a text relocation that generates a DT_TEXTREL segments in link phase.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-04 19:08:13 +00:00
Bill Schmidt
b453e16855 This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI.  The ABI will be updated with the new code sequence.

Former sequence:

  ld 9,x@got@tprel(2)
  add 9,9,x@tls

New sequence:

  addis 9,2,x@got@tprel@ha
  ld 9,x@got@tprel@l(9)
  add 9,9,x@tls

Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14 17:02:38 +00:00
Bill Schmidt
349c2787cf This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target.  This is the last of the four models, so we now have 
full TLS support.

This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.

As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly.  The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.

There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.

Bill


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-12 19:29:35 +00:00
Bill Schmidt
57ac1f458a This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:

     Instruction                            Relocation            Symbol
  addis ra,r2,x@got@tlsgd@ha           R_PPC64_GOT_TLSGD16_HA       x
  addi  r3,ra,x@got@tlsgd@l            R_PPC64_GOT_TLSGD16_L        x
  bl __tls_get_addr(x@tlsgd)           R_PPC64_TLSGD                x
                                       R_PPC64_REL24           __tls_get_addr
  nop
  <use address in r3>

The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation.  This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr.  Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation.  So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.

Most of the code is pretty straightforward.  I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call.  Something in the 
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations.  This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().

Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.

Comments welcome!

Thanks,
Bill


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 20:30:11 +00:00
Bill Schmidt
d7802bf0dd This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.

The patch includes code to handle external assembly and MC output with the
integrated assembler.  It intentionally does not support the "old" JIT.

For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:

 Code sequence            Relocation                  Symbol
  ld 9,x@got@tprel(2)      R_PPC64_GOT_TPREL16_DS      x
  add 9,9,x@tls            R_PPC64_TLS                 x

The register 9 is arbitrary here.  The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x.  It will replace x@tls with the thread-pointer
register (13).

The two test cases verify correct assembly output and relocation output
as just described.

PowerPC-specific selection node variants are added for the two
instructions above:  LD_GOT_TPREL and ADD_TLS.  These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS.  LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.

The rest of the processing is straightforward.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 16:18:08 +00:00
Bill Schmidt
34a9d4b3b9 This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer.  Additionally,
only TOC entries are addressed via the TOC pointer.

With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset.  Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed.  Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.

Consider a load of an external 4-byte integer.  With small code model, the
compiler generates:

	ld 3, .LC1@toc(2)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc ei[TC],ei

With medium model, it instead generates:

	addis 3, 2, .LC1@toc@ha
	ld 3, .LC1@toc@l(3)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc ei[TC],ei

Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer.  Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits.  Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.

Consider next a load of a function-scope static integer.  For small code
model, the compiler generates:

	ld 3, .LC1@toc(2)
	lwz 4, 0(3)

	.section	.toc,"aw",@progbits
.LC1:
	.tc test_fn_static.si[TC],test_fn_static.si
	.type	test_fn_static.si,@object
	.local	test_fn_static.si
	.comm	test_fn_static.si,4,4

For medium code model, the compiler generates:

	addis 3, 2, test_fn_static.si@toc@ha
	addi 3, 3, test_fn_static.si@toc@l
	lwz 4, 0(3)

	.type	test_fn_static.si,@object
	.local	test_fn_static.si
	.comm	test_fn_static.si,4,4

Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.

Note that it would be more efficient for the compiler to generate:

	addis 3, 2, test_fn_static.si@toc@ha
        lwz 4, test_fn_static.si@toc@l(3)

The current patch does not perform this optimization yet.  This will be
addressed as a peephole optimization in a later patch.

For the moment, the default code model for 64-bit PowerPC will remain the
small code model.  We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior.  Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.

I've tested the regression suite and the application/benchmark test suite in
two ways:  Once with the patch as submitted here, and once with additional
logic to force medium code model as the default.  The tests all compile
cleanly, with one exception.  The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers.  It just so happens
that small code model was incredibly lucky, in that temporary values in 
floating-point registers held the expected values needed by the external
library routine that was called incorrectly.  My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."

Here are a few comments on how the patch works, since the selection code
can be difficult to follow:

The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses.  These are expanded by SelectCodeCommon().  The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL.  These new node types correspond naturally to
the sequences described above.

The addis/ld sequence is generated for the following cases:
 * Jump table addresses
 * Function addresses
 * External global variables
 * Tentative definitions of global variables (common linkage)

The addis/addi sequence is generated for the following cases:
 * Constant pool entries
 * File-scope static global variables
 * Function-scope static variables

Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.

The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction.  Each of the instructions is converted to
a "real" PowerPC instruction.  When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).

I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a 
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL.  So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.

Note that for LDtocL, we generate a new form of LD called LDrs.  This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.

The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.

The above assumes use of an external assembler.  For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter.  Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.






git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27 17:35:46 +00:00
Ulrich Weigand
ba6086818d Add (some) PowerPC TLS relocation types to ELF.h and
generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13 19:24:36 +00:00
James Molloy
296815dcce Add support for ARM segment types PT_ARM_ARCHEXT, PT_ARM_EXIDX and PT_ARM_UNWIND.
Patch by Pete Chou!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 09:10:56 +00:00
Sid Manning
8ceffeb95c * Add e_flags enum for Hexagon
* Add Hexagon specific section indexes for small data
- Reviewed by Michael Spencer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30 02:26:15 +00:00
Roman Divacky
10a4318248 Add PowerPC64 relocation definitions. Patch by Adhemerval Zanella!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 16:38:02 +00:00
Roman Divacky
05b2bc8781 Revert r162034, r162035 and r162037.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 19:07:59 +00:00
Roman Divacky
dd4b9f3fe9 Add PPC64 relocations definitions, by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 18:31:29 +00:00
Simon Atanasyan
6aef977e85 Add some missed ELF constants definitions:
- section types
- dynamic table entries tags
- state flags for DT_FLAGS_1 entry

The patch reviewed by Rafael Espindola.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 14:12:32 +00:00