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3 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:27:25 +00:00
Chris Lattner
6f948be128 now that generic vector types aren't selected onto MMX registers, these 
tests don't need -disable-mmx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-19 20:12:58 +00:00
Mon P Wang
cab98e3168 Make isScalarToVector to return false if the node is a scalar. This will prevent 
DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-19 19:08:12 +00:00