Misha Brukman
a6ecd9ee47
Set the is64bit flag and propagate it to PowerPCRegisterInfo
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15671 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-11 23:45:43 +00:00
Misha Brukman
5b5708106e
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
2004-08-10 22:47:03 +00:00
Misha Brukman
3ada3e3f82
ADDI can take several forms, including:
...
addi r1, r2, 0
addi r1, <frame index #n>, 0
so we must check for the second parameter being a register for this instruction
to be considered a reg-to-reg copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15244 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-26 21:50:38 +00:00
Misha Brukman
8790d47453
assert() on MachineInstr properties instead of checking them dynamically
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15243 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-26 21:35:58 +00:00
Misha Brukman
774a297c83
* Recognize `addi r1, r2, 0' a move instruction
...
* List formats of instructions currently recognized as moves
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15242 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-26 21:29:00 +00:00
Misha Brukman
be15f67af7
Fix code formatting
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14899 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-16 20:54:25 +00:00
Misha Brukman
01d46e9c55
Implement PowerPCInstrInfo::isMoveInstr(), patch by Nate Begeman
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14898 91177308-0d34-0410-b5e6-96231b3b80d8
2004-07-16 20:51:55 +00:00
Misha Brukman
5dfe3a9c3b
Initial revision
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-06-21 16:55:25 +00:00
