Commit Graph

2073 Commits

Author SHA1 Message Date
Jim Grosbach
2727930ab4 ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:11:56 +00:00
Richard Barton
0a552d611e Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 09:43:18 +00:00
Jim Grosbach
54319e2a8c ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 21:17:34 +00:00
Jim Grosbach
94b590f8fa ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.

rdar://10550147

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 20:43:21 +00:00
Jim Grosbach
686c01854e MC: Unknown assembler directives are now hard errors.
Previously, an unsupported/unknown assembler directive issued a warning.
That's generally unsafe, and inconsistent with the behaviour of pretty
much every system assembler. Now that the MC assemblers are mature
enough to be the default on multiple targets, it's reasonable to
issue errors for these.

For target or platform directives that need to stay warnings, we
should add explicit handlers for them in, e.g., ELFAsmParser.cpp,
DarwinAsmParser.cpp, et. al., and issue the warning there.

rdar://9246275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 18:38:27 +00:00
Jim Grosbach
a9cc08f24f ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 23:51:36 +00:00
Richard Barton
04a09a461b Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 17:34:01 +00:00
Benjamin Kramer
71275b129b Missed some register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 12:21:46 +00:00
Benjamin Kramer
a356e9414c Update edis test for r155704.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-27 12:14:03 +00:00
Evan Cheng
cac31de146 Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 01:38:10 +00:00
Jim Grosbach
14ce6fac24 ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 22:40:08 +00:00
Kevin Enderby
24e767d076 Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 17:45:56 +00:00
Kevin Enderby
2c66edf434 Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24 15:55:00 +00:00
Jim Grosbach
c34954d432 ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155391 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 21:00:47 +00:00
Jim Grosbach
10a3933c5f Add ARM mode tests for the NEON vector shift-accumulate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155390 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 21:00:44 +00:00
Jim Grosbach
2b8525068a Tidy up. Reformat for ease of reading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155389 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-23 21:00:42 +00:00
Jim Grosbach
d8b3ed8f25 ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 18:12:54 +00:00
Jim Grosbach
181b147975 ARM some VFP tblgen'erated two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 00:15:00 +00:00
Jim Grosbach
bfb3c5a50c Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 00:14:57 +00:00
Silviu Baranga
35ee7d28a6 Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:18:57 +00:00
Silviu Baranga
6b9f97dd89 Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 14:09:07 +00:00
Silviu Baranga
fa1ebc6abe Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:12:50 +00:00
Silviu Baranga
e546c4c9c3 Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:02:55 +00:00
Silviu Baranga
9e71231309 Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 12:48:43 +00:00
Akira Hatanaka
ecdc9d5bb2 Add disassembler to MIPS.
Patch by Vladimir Medic. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 18:03:21 +00:00
Kevin Enderby
c5a2a33938 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-17 00:49:27 +00:00
Jim Grosbach
bf42f24e6e ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 23:00:25 +00:00
Jim Grosbach
68f89a6158 MC assembly parser handling for trailing comma in macro instantiation.
A trailing comma means no argument at all (i.e., as if the comma were not
present), not an empty argument to the invokee.

rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 21:18:49 +00:00
Akira Hatanaka
1fbfea7b06 This patch fixes 3 problems:
1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be
   ignored which in turn hid the next 2 problems:
2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and
   failed to do it's job of accepting all hex digits and:
3. The check for the hex values for the code instructions didn't account for
   blank separators.

Patch by Jack Carter. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:20:26 +00:00
Jim Grosbach
199366a6a6 ARM assembly two-operand forms for VRSHL.
rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:03:16 +00:00
Jim Grosbach
695eca66b1 Tidy up. Test formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:03:14 +00:00
Akira Hatanaka
3ef7edc77a Do not add offset in applyFixup. This has already been accounted for in Value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 18:00:19 +00:00
Jim Grosbach
705e2572b4 ARM two-operand aliases for VRHADD instructions.
rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 17:14:11 +00:00
Jim Grosbach
dbd6ba36e4 Tidy up. Testcase formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 17:14:07 +00:00
Richard Barton
d0c478d95f Add -disassemble support for -show-inst and -show-encode capability llvm-mc. Also refactor so all MC paraphernalia are created once for all uses as much as possible.
The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-16 11:32:10 +00:00
Kevin Enderby
b318cc16c9 Fixed a case of ARM disassembly getting an assert on a bad encoding
of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 22:40:17 +00:00
Jim Grosbach
1835547ec1 ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11222366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 17:40:18 +00:00
Jim Grosbach
6073b30b05 ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11221911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 16:53:25 +00:00
Evan Cheng
bee78fe5fc Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 05:33:07 +00:00
Charles Davis
0d82fe77f2 Add retw and lretw instructions. Also, fix Intel syntax parsing for all
ret instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 01:10:53 +00:00
Kevin Enderby
a69da35c12 Fix ARM disassembly of VLD instructions with writebacks.  And add test a case
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:25:40 +00:00
Jim Grosbach
a5378ebe78 ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:15:16 +00:00
Evan Cheng
82509e5c62 Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:13:00 +00:00
Jim Grosbach
a23ecc2ba9 ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.

rdar://11216577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10 17:31:55 +00:00
Craig Topper
e45cddfa08 Add the tests that were supposed to go with r153935 that I forgot svn add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06 07:09:59 +00:00
Jim Grosbach
4e53fe8dc6 ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.

rdar://11192734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 20:57:13 +00:00
Silviu Baranga
1c01249191 Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 16:19:29 +00:00
Silviu Baranga
82e1bba0e4 Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 16:13:15 +00:00
Jim Grosbach
22378fd664 ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 07:23:53 +00:00
Jim Grosbach
b657a90929 ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.

rdar://11153753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 03:17:53 +00:00