Craig Topper
|
ee62e4f6d1
|
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-10-16 16:50:08 +00:00 |
|
Craig Topper
|
b53fa8bf19
|
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-10-16 07:55:05 +00:00 |
|
Craig Topper
|
17730847d5
|
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-10-16 03:51:13 +00:00 |
|
Craig Topper
|
566f233ba6
|
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-10-15 20:46:47 +00:00 |
|
Craig Topper
|
6744a17dcf
|
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-10-04 06:30:42 +00:00 |
|
Evan Cheng
|
8c3fee5903
|
Refactor X86 target to separate MC code from Target code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
|
2011-07-25 18:43:53 +00:00 |
|