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Author SHA1 Message Date
Bruno Cardoso Lopes
a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 04:07:29 +00:00