Commit Graph

3241 Commits

Author SHA1 Message Date
Tim Northover
107cfa2169 TableGen: fix constness of new comparison function.
libc++ didn't seem to like a non-const call operator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 17:33:40 +00:00
Tim Northover
03f9197d62 TableGen: give asm match classes deterministic order.
TableGen was sorting the entries in some of its internal data
structures by pointer. This order filtered through to the final
matching table and affected the diagnostics produced on bad assembly
occasionally.

It also turns out STL algorithms are ridiculously easy to misuse on
containers with custom order methods. (No bugs before, or now that I
know of, but plenty in the middle).

This should fix the sanitizer bot, which ends up with weird pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 16:43:19 +00:00
Tim Northover
6dd670af75 AsmMatcher: emit subtarget feature enum in deterministic order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 16:43:16 +00:00
Benjamin Kramer
94ee55d4b3 Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 22:04:42 +00:00
Joey Gouly
715d98d657 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-12 10:28:05 +00:00
Benjamin Kramer
209a8c8e35 llvm-tblgen: Mangle operand replacements into the strings in printAliasInstr.
Cuts down the bloat in the AArch64 asm writer a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 15:42:16 +00:00
Benjamin Kramer
71faecf16f llvm-tblgen: Stabilize subreg index tables.
Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 11:22:26 +00:00
Vincent Lejeune
d8f2eb301c TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-03 19:43:28 +00:00
Jim Grosbach
ff372dc18d Tidy up. Comment grammar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 22:41:43 +00:00
Jim Grosbach
dd46230062 Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 22:41:39 +00:00
Craig Topper
aae60d1dc4 Move StringToOffsetTable into the TableGen include directory so I can use it in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-29 05:09:55 +00:00
Rui Ueyama
2957273b88 Option parsing: support case-insensitive option matching.
Re-submitting r189416 with fix for Windows build on where strcasecmp is not defined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 20:04:31 +00:00
Craig Topper
862b504201 Add missing include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 07:03:02 +00:00
Rui Ueyama
1997734e37 Revert "Option parsing: support case-insensitive option matching." as it broke Windows buildbot.
This reverts r189416.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:02:06 +00:00
Rui Ueyama
055f4e99ff Option parsing: support case-insensitive option matching.
Link.exe's command line options are case-insensitive. This patch
adds a new attribute to OptTable to let the option parser to compare
options, ignoring case.

Command lines are generally case-insensitive on Windows. CL.exe is an
exception. So this new attribute should be useful for other commands
running on Windows.

Differential Revision: http://llvm-reviews.chandlerc.com/D1485

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-27 23:47:01 +00:00
Jakob Stoklund Olesen
d93969c32a Add an OtherPreserved field to the CalleeSaved TableGen class.
This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.

This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-23 02:25:47 +00:00
Elena Demikhovsky
1765e74c15 AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 12:18:28 +00:00
Tim Northover
f7ab3a84b3 ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.

TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-22 09:57:11 +00:00
Aaron Ballman
3369599db2 Fixing a warning about control reaching the end of a non-void function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-16 01:43:31 +00:00
Jack Carter
0fe3792a2f [Mips][msa] Value types for MSA support.
Added v8f16 to ValueTypes.h, ValueTypes.cpp, ValueTypes.td, 
and CodeGenTarget.cpp

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188326 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-13 22:34:26 +00:00
Richard Sandiford
1f85736c97 Revert r188164: Stablize MCK_Reg ordering in AsmMatcherEmitter
Apparently caused a failure on Darwin


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:57:51 +00:00
Richard Sandiford
dfb5ceae90 Stablize MCK_Reg ordering in AsmMatcherEmitter
clang bootstraps intermittently failed for me due a difference in
the MCK_Reg ordering in ARMGenAsmMatcher.inc.  E.g. in my latest
run the stage 1 and stage 3 versions were the same but the stage 2
one was different (though still functionally correct).  This meant
that the .o comparison failed.

MCK_Regs were assigned by iterating over a std::set< std::set<Record*> >,
and since std::set is sorted lexicographically, the order depended on the
order of the pointer values.  This patch replaces the pointer ordering
with LessRecordByID.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188164 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-12 10:39:45 +00:00
Reid Kleckner
47cfec0284 Remove some std stream usage from Support and TableGen
LLVM's coding standards recommend raw_ostream and MemoryBuffer for
reading and writing text.

This has the side effect of allowing clang to compile more of Support
and TableGen in the Microsoft C++ ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 22:51:21 +00:00
Vladimir Medic
588f408b95 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:25:27 +00:00
Hans Wennborg
a15d5db7f2 Option parsing: remove non-SUPPORT_ALIASARGS fall-back
The clients of this code have been updated to all support AliasArgs.

This depends on Clang r187538 and lld r187541.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 23:28:51 +00:00
Hans Wennborg
9dd8c0cffe Option parsing: add support for alias arguments.
This makes option aliases more powerful by enabling them to
pass along arguments to the option they're aliasing.

For example, if we have a joined option "-foo=", we can now
specify a flag option "-bar" to be an alias of that, with the
argument "baz".

This is especially useful for the cl.exe compatible clang driver,
where many options are aliases. For example, this patch enables
us to alias "/Ox" to "-O3" (-O is a joined option), and "/WX" to
"-Werror" (again, -W is a joined option).

Differential Revision: http://llvm-reviews.chandlerc.com/D1245

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 22:44:41 +00:00
Andrew Trick
d3d751804c comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 21:05:54 +00:00
Tom Stellard
5519dc9de8 Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 20:43:08 +00:00
Vincent Lejeune
2ca1e4a39c TableGen: Enumerate Schedule Model too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187511 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 19:31:20 +00:00
Andrew Trick
c408335bf5 Fix register pressure tables on ARM.
The heuristic that merges register pressure sets was bogus for ARM's S/D regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:31 +00:00
Andrew Trick
bbf20d4d4a Add tracing to the tblgen register pressure table generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 03:24:28 +00:00
Craig Topper
d953bcd487 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187333 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 21:28:02 +00:00
Elena Demikhovsky
dc8a318f44 fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187325 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:45:12 +00:00
Elena Demikhovsky
c18f4efc5d Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-28 08:28:38 +00:00
Aaron Ballman
a946190351 Using a different loop induction variable than the enclosing scope. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187159 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 22:09:31 +00:00
Justin Holewinski
563a9cf7ba Fix a bug in TableGen where the intrinsic function name recognizer could mis-identify names if one was a prefix substring of the other
For two intrinsics 'llvm.nvvm.texsurf.handle' and 'llvm.nvvm.texsurf.handle.internal',
TableGen was emitting matching code like:

  if (Name.startswith("llvm.nvvm.texsurf.handle")) ...
  if (Name.startswith("llvm.nvvm.texsurf.handle.internal")) ...

We can never match "llvm.nvvm.texsurf.handle.internal" here because it will
always be erroneously matched by the first condition.

The fix is to sort the intrinsic names and emit them in reverse order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 12:32:00 +00:00
Andrew Trick
bba663e30a RegPressure: Order the "pressure sets" by number of regunits per set.
This lets heuristics easily pick the most important set to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 07:26:29 +00:00
Craig Topper
f63ef914b6 Split generated asm mnemonic matching table into a separate table for each asm variant.
This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-24 07:33:14 +00:00
Craig Topper
349d6a70a1 Remove 'else' after 'return'. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186929 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:27:36 +00:00
Craig Topper
00f94955ef Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186928 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 06:25:00 +00:00
Vladimir Medic
9273151c3b This patch allows targets to define weather the instruction mnemonics in asm matcher tables will contain '.' character.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186388 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 09:22:38 +00:00
Aaron Ballman
54911a5303 Teaching llvm-tblgen to not emit a switch statement when there are no case statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 16:53:32 +00:00
Craig Topper
3c70fcf02b Add 'const' qualifier to some arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186312 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-15 08:02:13 +00:00
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Nick Lewycky
dc89737bcd Extend 'readonly' and 'readnone' to work on function arguments as well as
functions. Make the function attributes pass add it to known library functions
and when it can deduce it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-06 00:29:58 +00:00
Craig Topper
6227d5c690 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-04 01:31:24 +00:00
Chad Rosier
b7110cf5b5 Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.

The current algorithm, LessRecord, uses the StringRef compare_numeric
function.  This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:

  T1
  T1_W
  T1_X
  T1_XYZW
  T1_Y
  T1_Z
  T2
  T2_W
  T2_X
  T2_XYZW
  T2_Y
  T2_Z

In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another.  However, in other parts
of the register bank, the scaling factors are different:

dEnum/dN = 5:
  KC0_128_W
  KC0_128_X
  KC0_128_XYZW
  KC0_128_Y
  KC0_128_Z
  KC0_129_W
  KC0_129_X
  KC0_129_XYZW
  KC0_129_Y
  KC0_129_Z

The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'.  This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1.  For example, the registers are now sorted as
follows:

  T1
  T2
  T3
  ...
  T0_W
  T1_W
  T2_W
  ...
  T0_X
  T1_X
  T2_X
  ...
  KC0_128_W
  KC0_129_W
  KC0_130_W
  ...

For the Mips and R600 I see a 19% and 6% reduction in size, respectively.  I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes).  I suspect there will be even
greater wins for targets with larger register files.

Patch reviewed by Jakob.
rdar://14006013


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-27 19:38:13 +00:00
Tom Stellard
898b9f020d TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.

In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.

For example, if you have an instruction like:

def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;

You can look up the operand indices using the new function, like this:

Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst)  => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2

The operand names are case sensitive, so $dst and $DST are considered
different operands.

This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values.  These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 21:22:09 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 17:08:10 +00:00
Andrew Trick
a3d82ce19f Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:06 +00:00