Commit Graph

10 Commits

Author SHA1 Message Date
Dan Gohman
334190e47e Remove the explicit request for "Latency" scheduling from MSP430,
as the Latency scheduler is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 17:53:16 +00:00
Chris Lattner
0a9481f44f Enhance ComputeMaskedBits to know that aligned frameindexes
have their low bits set to zero.  This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively.  Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST).  The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-13 22:25:43 +00:00
Owen Anderson
765fd9c62d CombinerAA is now reordering these stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:56:29 +00:00
Chris Lattner
d1b7382983 Fix some issues in WalkChainUsers dealing with
CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02 22:20:06 +00:00
Anton Korobeynikov
f32df4ce3e Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
Yay for ASCII graphics!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84808 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 00:16:00 +00:00
Anton Korobeynikov
a91f4c561e Add DAG printing for RMW stuff debugging
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84776 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 19:18:28 +00:00
Anton Korobeynikov
83fceb9481 RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-21 19:17:55 +00:00
Benjamin Kramer
90869455b5 Eliminate some redundant llvm-as calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83837 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-12 09:31:55 +00:00
Anton Korobeynikov
436604d505 Add missed mem-mem move patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-11 23:03:53 +00:00
Anton Korobeynikov
afac8abfc0 Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83811 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-11 23:03:28 +00:00