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5 Commits

Author SHA1 Message Date
Evan Cheng
c4c6257c1a Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-13 23:20:37 +00:00
Duraid Madina
badf0d9614 add bundling! well not really, for now it's just stop-insertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25593 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 02:23:38 +00:00
Duraid Madina
f2db9b88da DAG->DAG instruction selection for ia64! "hello world" works, not much else. 
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24058 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-28 17:46:35 +00:00
Misha Brukman
4633f1cde8 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21424 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-21 23:13:11 +00:00
Duraid Madina
9b9d45f60e and so it begins... 
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20652 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-17 18:17:03 +00:00