Duncan Sands
fea3b218d6
Move Sub simplifications and additional Add simplifications out of
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instcombine and into InstructionSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121861 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 14:07:39 +00:00
Duncan Sands
f8b1a5ea96
If we detect that the instruction we are simplifying is unreachable, arrange for
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it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 11:02:22 +00:00
Frits van Bommel
26e097ca4b
Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
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When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 09:51:20 +00:00
Bill Wendling
22447ae54b
Add fixups for Thumb LDR/STR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 08:51:02 +00:00
Rafael Espindola
2bf6afc277
Relax alignment fragments.
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With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).
This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 08:45:53 +00:00
Rafael Espindola
f9a4476173
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.
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Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 07:39:29 +00:00
Chris Lattner
9448184b99
add another overflow idiom
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 07:28:58 +00:00
Chris Lattner
08859ffa63
add a note about overflow idiom recognition.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121853 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 07:25:55 +00:00
Rafael Espindola
b35d56c2fe
Generalize an assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 07:12:24 +00:00
Chris Lattner
ef17f08dbc
add a shift/imul missed optimization
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 07:10:43 +00:00
Chris Lattner
2fc36e19b1
add a note about a SPEC hack that gcc mainline does.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121849 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 06:38:24 +00:00
Chris Lattner
33e77d3cb9
take care of some todos, transforming [us]mul_lohi into
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a wider mul if the wider mul is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 06:04:19 +00:00
Chris Lattner
1a0fbe2cf4
when transforming a MULHS into a wider MUL, there is no need to SRA the
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result, the top bits are truncated off anyway, just use SRL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 05:51:39 +00:00
Chris Lattner
ba3c815570
make qsort predicate more conformant by returning 0 for equal values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 04:52:41 +00:00
Bill Wendling
bc4224bc6b
Reapply r121808 now that the missing patterns have been supplied.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e
Add some missing patterns now that tLDRB and tLDRH are split into reg and
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immediate versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:58:57 +00:00
Owen Anderson
86e8a700f5
Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
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this case involve a select that simplifies to itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:55:35 +00:00
Owen Anderson
93f83deba1
Cleanup trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121816 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:52:44 +00:00
Bill Wendling
7d1d8db54a
Revert r121808 until I can fix the build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5
thumb adr fixup needs alignment just like the t2 version.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475
Comments and cleaning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
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particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:40:49 +00:00
Jakob Stoklund Olesen
257c556d85
Simplify RegAllocGreedy's use of register aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121807 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:38:19 +00:00
Jakob Stoklund Olesen
eb7464ebda
Simplify CCState's use of register aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:28:01 +00:00
Jakob Stoklund Olesen
597faa8f1f
Simplify AggressiveAntiDepBreaker's use of register aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:23:15 +00:00
Jakob Stoklund Olesen
16999da951
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 23:10:48 +00:00
Jim Grosbach
d40963c406
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215
Multiclassify the LDR/STR encoding patterns. The only functionality difference
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is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 22:10:49 +00:00
Evan Cheng
bbc726d624
Fix a minor bug in two-address pass. It was missing a commute opportunity.
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regB = move RCX
regA = op regB, regC
RAX = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
movl %edi, %eax
shlq $32, %rcx
leaq (%rcx,%rax), %rax
=>
movl %edi, %eax
shlq $32, %rcx
orq %rcx, %rax
rdar://8762995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:34:53 +00:00
Jim Grosbach
8d6d7d6e30
trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:28:29 +00:00
Matt Beaumont-Gay
3ef9f3da39
Move debugging code entirely within DEBUG(). Silences an unused variable
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warning in the opt build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:14:55 +00:00
Jim Grosbach
40edf73a62
Refactor a bit for legibility.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e
trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150
Make sure to propagate the predicate operands for LEApcrel to ADR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 19:42:53 +00:00
Jakob Stoklund Olesen
bfce678de7
Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121783 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 19:38:49 +00:00
Jakob Stoklund Olesen
4a84cce3ed
Use TRI::printReg instead of AbstractRegisterDescription when printing
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LiveIntervalUnions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 18:53:47 +00:00
Jakob Stoklund Olesen
414e5023f8
Add TargetRegisterInfo::printReg() to pretty-print registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 18:53:39 +00:00
Jim Grosbach
4750020788
ARM Fixups relative to thumb functions need to have the low bit of the value
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set for interworking to work properly. rdar://8755956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 18:46:57 +00:00
Jakob Stoklund Olesen
d84de8cf62
Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 17:47:36 +00:00
Daniel Dunbar
abfbac52df
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 17:37:16 +00:00
Jim Grosbach
e8eb1ea6ac
Trailing whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 16:25:15 +00:00
Bill Wendling
971321bb70
Use the integer scheduling intrinsic for integer loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 12:33:05 +00:00
Chris Lattner
3aff13b82a
- Insert new instructions before DomBlock's terminator,
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which is simpler than finding a place to insert in BB.
- Don't perform the 'if condition hoisting' xform on certain
i1 PHIs, as it interferes with switch formation.
This re-fixes "example 7", without breaking the world hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121764 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 08:46:09 +00:00
Chris Lattner
60d410d7bb
fix two significant issues with FoldTwoEntryPHINode:
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first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.
second, it doesn't clean up the "if diamond" that it just
eliminated away. This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121762 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 08:01:53 +00:00
Chris Lattner
071edc81f2
remove the instsimplify logic I added in r121754. It is apparently
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breaking the selfhost builds, though I can't fathom how.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:53:03 +00:00
Chris Lattner
44da7ca421
clean up logic, convert std::set to SmallPtrSet, handle the case
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when all 2-entry phis are simplified away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:41:39 +00:00
Chris Lattner
e0b18e5912
tidy up a bit, move DEBUG down to when we commit to doing the transform so we
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don't print it unless the xform happens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121758 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:23:10 +00:00
Chris Lattner
07ff3539f5
use SimplifyInstruction instead of reimplementing part of it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:20:29 +00:00
Chris Lattner
995ba1bd49
simplify GetIfCondition by using getSinglePredecessor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:15:21 +00:00
Chris Lattner
6de0a28dfb
use AddPredecessorToBlock in 3 places instead of a manual loop.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:09:42 +00:00
Chris Lattner
73c50a68a7
make FoldTwoEntryPHINode use instsimplify a bit, make
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GetIfCondition faster by avoiding pred_iterator. No
really interesting change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 07:00:00 +00:00
Chris Lattner
2112bbc42d
remove the dead (and terrible) llvm::RemoveSuccessor function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121753 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 06:51:55 +00:00
Chris Lattner
302ba6fc1c
improve DEBUG's a bit, switch to eraseFromParent() to simplify
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code a bit, switch from constant folding to instsimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 06:17:25 +00:00
Chris Lattner
117f8cffc5
reapply my recent change that disables a piece of the switch formation
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work, but fixes 400.perlbmk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 05:57:30 +00:00
Bill Wendling
f4caf69720
The tLDR et al instructions were emitting either a reg/reg or reg/imm
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:36:38 +00:00
Evan Cheng
0c1aec1891
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 03:22:07 +00:00
Jakob Stoklund Olesen
885b3283ea
Remove unused vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:58:47 +00:00
Jakob Stoklund Olesen
46c83c80c5
Try reassigning all virtual register interferences, not just those with lower
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spill weight. Filter out fixed registers instead.
Add support for reassigning an interference that was assigned to an alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:37:49 +00:00
Jakob Stoklund Olesen
b64d92e29f
Add stub for RAGreedy::trySplit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:37:44 +00:00
Owen Anderson
a838a25d59
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
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process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14 00:36:49 +00:00
Owen Anderson
2d9220e8f5
Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state
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where I'm confident there were no crashes or miscompilations. XFAIL the test added since then for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121733 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:49:28 +00:00
Jason W Kim
3fa4c1dc95
First cut of ARM/MC/ELF PIC relocations.
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Test has fixme, to move to .s -> .o test when AsmParser works better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:16:07 +00:00
Bob Wilson
4711d5cda3
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:37 +00:00
Bob Wilson
0e6d540d17
Simplify N2VSPat, removing some unnecessary type arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121729 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:31 +00:00
Chris Lattner
f9a1b2a4cf
temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 23:02:19 +00:00
Dan Gohman
c1f1efdd1a
Update a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:53:18 +00:00
Owen Anderson
6b8719fd7d
Revert r121721, which broke buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:51:08 +00:00
Dan Gohman
0f7f194416
Reapply r121520, PartialAlias implementation for BasicAA, now that
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memdep is updated to handle it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:50:24 +00:00
Dan Gohman
2cd1952917
Update memdep to handle PartialAlias as MayAlias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121723 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:47:57 +00:00
Owen Anderson
e8d02539d7
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
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which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:29:52 +00:00
Bob Wilson
4dedddce93
Delete a line that I forgot to revert previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121719 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 22:05:55 +00:00
Bob Wilson
1e6f59608b
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
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Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:58:05 +00:00
Bob Wilson
3a6756cb1c
Use pseudo instructions for 2-register Neon instructions for scalar FP.
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Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:52 +00:00
Bob Wilson
6dbcea1f8e
Remove unused instruction class arguments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121715 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 21:05:44 +00:00
Evan Cheng
30fb13f97a
Generalize BFI isel lowering a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 20:32:54 +00:00
Chris Lattner
94c58a0906
add some DEBUG's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:55:30 +00:00
Owen Anderson
c266600bec
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
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as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:31:11 +00:00
Jim Grosbach
56a2535474
Use 32-bit types for 32-bit values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:25:46 +00:00
Jim Grosbach
7e294cfcf9
Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121708 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 19:18:13 +00:00
Benjamin Kramer
cf8b3257c0
Fix sort predicate. qsort(3)'s predicate semantics differ from std::sort's. Fixes PR 8780.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 18:20:38 +00:00
Chris Lattner
de1c3605a6
Add a couple dag combines to transform mulhi/mullo into a wider multiply
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when the wider type is legal. This allows us to compile:
define zeroext i16 @test1(i16 zeroext %x) nounwind {
entry:
%div = udiv i16 %x, 33
ret i16 %div
}
into:
test1: # @test1
movzwl 4(%esp), %eax
imull $63551, %eax, %eax # imm = 0xF83F
shrl $21, %eax
ret
instead of:
test1: # @test1
movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F
mulw 4(%esp)
andl $65504, %edx # imm = 0xFFE0
movl %edx, %eax
shrl $5, %eax
ret
Implementing rdar://8760399 and example #4 from:
http://blog.regehr.org/archives/320
We should implement the same thing for [su]mul_hilo, but I don't
have immediate plans to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 08:39:01 +00:00
Chris Lattner
a9f6bbea62
reinstate my patch: the miscompile was caused by an inverted branch in the
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'and' case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121695 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 08:12:19 +00:00
Chris Lattner
92407e5895
Completely disable the optimization I added in r121680 until
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I can track down a miscompile. This should bring the buildbots
back to life
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 07:41:29 +00:00
Chris Lattner
11ae9e29a9
remove the verbose-asm "constant pool double" comments that we were printing
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for each constant pool entry. Using WriteTypeSymbolic here takes time
proportional to the size of the module, for each constant pool entry.
This speeds up -verbose-asm llc on 252.eon (a random testcase at my disposal)
from 4.4s to 2.137s. llc takes 2.11s with asm-verbose off, so this is now a
pretty reasonable cost for verbose comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 07:35:47 +00:00
Chris Lattner
daa02ab70c
Make simplifycfg reprocess newly formed "br (cond1 | cond2)" conditions
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when simplifying, allowing them to be eagerly turned into switches. This
is the last step required to get "Example 7" from this blog post:
http://blog.regehr.org/archives/320
On X86, we now generate this machine code, which (to my eye) seems better
than the ICC generated code:
_crud: ## @crud
## BB#0: ## %entry
cmpb $33, %dil
jb LBB0_4
## BB#1: ## %switch.early.test
addb $-34, %dil
cmpb $58, %dil
ja LBB0_3
## BB#2: ## %switch.early.test
movzbl %dil, %eax
movabsq $288230376537592865, %rcx ## imm = 0x400000017001421
btq %rax, %rcx
jb LBB0_4
LBB0_3: ## %lor.rhs
xorl %eax, %eax
ret
LBB0_4: ## %lor.end
movl $1, %eax
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 07:00:06 +00:00
Chris Lattner
021c9d3bd4
make this logic a bit simpler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 06:36:51 +00:00
Chris Lattner
3d5121314a
split all the guts of SimplifyCFGOpt::run out into one function
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per terminator kind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121688 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 06:25:44 +00:00
Chris Lattner
97bd89ece3
fix a bug in r121680 that upset the various buildbots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:34:18 +00:00
Chris Lattner
979b8f1d8c
refactor the speculative execution logic to be factored into the cond branch code instead of
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doing a cfg search for every block simplified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121686 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:26:52 +00:00
Chris Lattner
eff7edf126
simplify a bunch of code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:20:28 +00:00
Chris Lattner
ef5002ba85
move HoistThenElseCodeToIf up to a more logical and efficient-to-handle place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:15:29 +00:00
Chris Lattner
ddb97a2bf1
move 'MergeBlocksIntoPredecessor' call earlier. Use
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getSinglePredecessor to simplify code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:10:48 +00:00
Chris Lattner
97fdb898f5
factor new code out to a SimplifyBranchOnICmpChain helper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121681 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 05:03:41 +00:00
Chris Lattner
7312a22ed6
enhance the "change or icmp's into switch" xform to handle one value in an
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'or sequence' that it doesn't understand. This allows us to optimize
something insane like this:
int crud (unsigned char c, unsigned x)
{
if(((((((((( (int) c <= 32 ||
(int) c == 46) || (int) c == 44)
|| (int) c == 58) || (int) c == 59) || (int) c == 60)
|| (int) c == 62) || (int) c == 34) || (int) c == 92)
|| (int) c == 39) != 0)
foo();
}
into:
define i32 @crud(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
entry:
%cmp = icmp ult i8 %c, 33
br i1 %cmp, label %if.then, label %switch.early.test
switch.early.test: ; preds = %entry
switch i8 %c, label %if.end [
i8 39, label %if.then
i8 44, label %if.then
i8 58, label %if.then
i8 59, label %if.then
i8 60, label %if.then
i8 62, label %if.then
i8 46, label %if.then
i8 92, label %if.then
i8 34, label %if.then
]
by pulling the < comparison out ahead of the newly formed switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 04:50:38 +00:00
Chris Lattner
0aa749bde7
merge two very similar functions into one that has a bool argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121678 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 04:26:26 +00:00
Evan Cheng
de7f920835
Disable auto-detection of AVX support since AVX codegen support is not ready.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 04:23:53 +00:00
Chris Lattner
662269d2ab
don't bother handling non-canonical icmp's
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121676 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 04:18:32 +00:00
Chris Lattner
803a29d19f
inline a function, making the result much simpler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 04:15:19 +00:00