Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
* Change getVarInfo to take real virtual register numbers and offset them
itself. This has caused me so much grief, it's not even funny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6115 91177308-0d34-0410-b5e6-96231b3b80d8
