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Author SHA1 Message Date
Chad Rosier
649326ab15 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:14:52 +00:00
Chad Rosier
8d0447c506 Fix a couple of copy-n-paste bugs. Noticed by George Russell! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 18:56:22 +00:00
Manuel Klimek
84cbb6f00d Changes the JSON parser to use the SourceMgr. 
Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 18:16:39 +00:00
Rafael Espindola
edae8e1e4d Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:00:36 +00:00
Rafael Espindola
d4304031cb Add const. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147054 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 14:48:04 +00:00
Rafael Espindola
c677e790e5 Small refactoring so that RelocNeedsGOT can stay in the target independent 
side when the target specific bits are moved to the Target directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147053 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 14:26:29 +00:00
Manuel Klimek
9a31fb0c38 Removes unused field TheError from LLLexer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 10:02:45 +00:00
Craig Topper
224c1b275d Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df Fix typo in a couple comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 06:30:53 +00:00
Nick Lewycky
20aded5912 A call to a function marked 'noinline' is not an inline candidate. The sole 
call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147037 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 06:06:30 +00:00
Nick Lewycky
8369687576 Make some intrinsics safe to speculatively execute. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147036 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 05:52:02 +00:00
Evan Cheng
1e33e8b715 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99 ARM assembly parsing allows constant expressions for lane indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 01:19:23 +00:00
Eric Christopher
f33ab86aad Regenerate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:52:44 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc Expand 64-bit CTPOP and CTTZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82 Expand 64-bit atomic load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
cf966cb0c3 Test case for r147017. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147018 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:58:36 +00:00
Akira Hatanaka
c0ea04389c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6 64-bit uint-fp conversion nodes are expanded. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f Set the correct stack pointer register that should be saved or restored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:28:36 +00:00
Jim Grosbach
06d738c76a Enable and fix a test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:20:00 +00:00
Chris Lattner
1a31f3b90c Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on 
the build bot in some cases.  The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type.  It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext.  We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.

Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is 
pretty great that way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:14:57 +00:00
Jim Grosbach
aee718beac ARM .req register name aliases are case insensitive, just like regnames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2fd0475cdb Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2 64-bit data directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86 32-to-64-bit sext_inreg pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a Add 64-bit extload patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:33:53 +00:00
Jim Grosbach
3cbe43fe69 Move comment to appropriate place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
990d639f55 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
05c585319b Revert part of r146995 that was accidentally commmitted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
403992dc58 32-to-64-bit sign extension pattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
caace8abdf Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 21:50:49 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Lang Hames
aa13482784 Fix assert condition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146987 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:23:40 +00:00
Jakub Staszak
25101bb2a7 Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:03:10 +00:00
Jim Grosbach
514806b52e ARM enable a few more tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:03:00 +00:00
Devang Patel
45ca049f1f Add support to add named metadata operand. 
Patch by Andrew Wilkins!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146984 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:29:36 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
ba4f83b4e9 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 13:34:28 +00:00